Semiconductor memory device capable of suppressing peak current

Details Semiconductor memory device capable of suppressing peak current Semiconductor memory device capable of suppressing peak current

2008-07-24

2010-12-21

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Floating gate

Multiple values

C365S185170, C365S220000, C710S066000

Reexamination Certificate

active

07855914

ABSTRACT:
A memory cell array includes a plurality of memory cells, in which n (n is a natural number equal to 3 or larger) cells are simultaneously written. A control circuit controls the memory cell array. A conversion circuit converts data constituted of k (k is equal to n or smaller, and is a natural number equal to 3 or larger) bits stored in the memory cells into data of h (h is equal to k or larger, and is a natural number equal to 2 or larger) bits on the basis of a conversion rule.

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