Semiconductor memory device capable of shortening erase time

Details Semiconductor memory device capable of shortening erase time Semiconductor memory device capable of shortening erase time

2011-08-09

2011-08-09

Dinh, Son (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220, C365S185290

Reexamination Certificate

active

07995392

ABSTRACT:
In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≦n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.

REFERENCES:
patent: 6714459 (2004-03-01), Hirano
patent: 6714541 (2004-03-01), Iyer et al.
patent: 7068541 (2006-06-01), Sakamoto et al.
patent: 7233529 (2007-06-01), Matsubara et al.
patent: 2005-24248 (2005-03-01), None
Office Action issued Jan. 3, 2011, in Korean Patent Application No. 10-2008-125817, with English translation. 9 pages.

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