Semiconductor memory device capable of rewriting data signal

Details Semiconductor memory device capable of rewriting data signal Semiconductor memory device capable of rewriting data signal

2002-05-06

2004-04-27

Nelms, David (Department: 2818)

Static information storage and retrieval

Magnetic bubbles

Disposition of elements

C365S230060, C365S230080, C365S189011, C365S191000

Reexamination Certificate

active

06728122

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to a semiconductor memory device capable of rewriting a data signal.
2. Description of the Background of Art
FIG. 20
is a circuit block diagram showing a main section of a prior art dynamic random access memory (hereinafter referred to as DRAM).
In
FIG. 20
, this DRAM has two memory cell arrays MA
1
and MA
2
. Each of memory cell arrays MA
1
and MA
2
includes memory cells MC located at respective intersections between word lines WL and bit line pairs BL and /BL. Memory cell MC stores one data signal thereon.
Bit line equalize circuits
82
and
83
are provided to bit line pairs BL and /BL of respective memory cell arrays MA
1
and MA
2
. Bit line equalize circuits
82
and
83
are activated in response to transition of respective bit line equalize signals BLEQL and BLEQR to L level, which is an active level, to precharge corresponding bit line pair BL and /BL to bit line precharge potential VBL (=VCC/2).
A transfer gate
80
is provided between a pair of bit lines BL and /BL of memory cell array MA
1
and a pair of nodes N
81
and N
82
; and a transfer gate
81
is provided between a pair of bit lines BL and /BL of memory cell array MA
2
and a pair of nodes N
81
and N
82
. Transfer gates
80
and
81
become non-conductive in response to transition of signals BLIL and BLIR to L level.
Nodes N
81
and N
82
are connected to a sense amplifier
84
. Sense amplifier
84
is activated in response to transition of sense amplifier activation signals SE and /SE to H level and L level, respectively, to amplify a small potential difference occurring between nodes N
81
and N
82
to power supply voltage VCC. Nodes N
81
and N
82
are connected to one ends of global IO lines GIO and /GIO through a column select gate
85
. Column select gate
85
becomes conductive in response to transition of a corresponding column select line CSL to H level, which is a select level.
A GIO line equalize circuit
86
, a read amplifier
87
and a write driver
88
are connected to the other ends of global
10
line pair GIO and /GIO. GIO line equalize circuit
86
is activated in response to transition of GIO line equalize signal GIOEQ to L level, which is an active level, to precharge global IO lines GIO and /GIO to power supply potential VCC. Read amplifier
87
is activated in response to transition of a signal PAE to H level, which is an active level, to compare potentials of global lines GIO and /GIO in magnitude with each other and to output a read data signal RD at a logical level corresponding to a result of the comparison.
Write driver
88
is activated in response to transition of a write driver activation signal WDE to H level, which is an active level, to drive one of global IO lines GIO and /GIO to H level and in addition, the other to L level according to a logical level of a write data signal WD.
That is, write driver
88
, as shown in
FIG. 21
, includes: NAND gates
91
and
92
; inverters
93
to
97
; P channel MOS transistors
98
and
99
; and N channel MOS transistors
100
and
101
. P channel MOS transistors
98
and
99
are connected between power supply potential VCC line and each of respective global lines GIO and /GIO; and N channel MOS transistors
100
and
101
are connected between each of respective global IO lines GIO and /GIO and ground potential GND line.
Write driver activation signal WDE is inputted to one input nodes of NAND gates
91
and
92
. Write data signal WD is inputted directly to the other input node of NAND gate
91
and in addition, to the other input node of NAND gate
92
through inverter
93
. An output signal of NAND gate
91
is inputted to the gate of P channel MOS transistor
98
through inverters
94
and
95
, and in addition, to the gate of N channel MOS transistor
101
through inverter
94
. An output signal of NAND gate
92
is inputted to the gate of N channel MOS transistor
100
through inverter
95
and in addition, to the gate of P channel MOS transistor
99
through inverters
96
and
97
.
In write operation and in a case where no rewriting of data is inhibited by a write mask signal, write driver activation signal WD is driven to H level, which is an active level, and NAND gates
91
and
92
operate as inverters. In a case where write data signal WD is at H level, MOS transistors
98
and
101
become conductive and in addition, MOS transistors
99
and
100
become non-conductive, and global IO lines GIO and /GIO are driven to H level and L level, respectively. In a case where write data signal WD is at L level, MOS transistors
99
and
100
become conductive and in addition, MOS transistors
98
and
101
become non-conductive, and global lines GIO and /GIO are driven to L level and H level, respectively.
Then, description will be given of an operation of DRAM shown in
FIGS. 20 and 21
. Note that of memory cell arrays MA
1
and MA
2
, memory cell array MA
1
is selected.
In write operation, bit line equalize signal BLEQL is first raised to H level to deactivate bit line equalize circuit
82
and in addition, array select signal BLIR is driven to L level to cause transfer gate
81
to be non-conductive. Then, word line WL is driven to H level, which is a select level, to activate memory cell MC and a small potential difference occurs between bit line pair BL and /BL according to stored data on memory cell MC.
Then, sense amplifier activation signals SE and /SE are driven to H level and L level, respectively, to activate sense amplifier
84
; and one bit line (for example, BL) is driven to H level and in addition, the other bit line (/BL in this case) is driven to L level. Subsequently, GIO line equalize signal GIOEQ is driven to H level, which is an inactive level, and GIO line equalize circuit
86
is deactivated to cease equalization of global IO lines GIO and /GIO.
Then column select line CSL is raised to H level, which is a select level, to cause column gate
85
to be conductive and potentials of bit lines BL and /BL are transmitted to respective global IO lines GIO and /GIO. Read amplifier
87
is activated in response to transition of signal PAE to H level, which is an active level, to compare potentials of global IO lines GIO and /GIO in magnitude and to output read data signal RD at a logical level corresponding to a result of the comparison.
In write operation, similar to a read operation, bit line equalize circuit
82
is deactivated, transfer gate
81
is caused to be non-conductive, sense amplifier
84
is activated to drive one bit line to H level and in addition, the other bit line to L level, and GIO line equalize circuit
86
is deactivated to cease equalization of global IO line pair GIO and /GIO.
Then, write driver activation signal WDE is driven to H level, which is an active level, to activate write driver
88
; and one of global IO lines GIO and /GIO is driven to H level, and the other is driven to L level according to a logical level of write data signal WD. Subsequently, column select line CSL is driven to H level, which is a select level, to cause column select gate
85
to be conductive and potentials of global IO lines GIO and /GIO are transmitted to bit lines BL and /BL to write a potential of a bit line (BL in the figure) onto memory cell MC.
In a prior art DRAM, however, bit line pair BL and /BL and global IO line pair GIO and /GIO are connected directly to each other through column select gate
85
; therefore, there has been a problem that in a case where precharge of global
10
line pair GIO and /GIO is incomplete, or in a case where noise occurs on global IO line pair GIO and /GIO by interference from other wirings, a data signal read-out onto bit line pair BL and /BL is destroyed. Although there is a method to enhance a current drive ability of sense amplifier
84
as a measure to prevent a data signal read-out onto bit line pair BL and /BL from being destroyed, a problem of increase in a layout area of sense amplifier
84
still remains.
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