Semiconductor memory device capable of repairing small leak...

Details Semiconductor memory device capable of repairing small leak... Semiconductor memory device capable of repairing small leak...

2001-02-27

2002-10-15

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Powering

Data preservation

C365S227000, C365S226000, C365S188000, C365S174000

Reexamination Certificate

active

06466506

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device capable of specifying and replacing a memory cell including a small leak failure, thereby realizing an improved yield.
2. Description of the Background Art
A semiconductor memory device, especially, a static random access memory (SRAM) has features of easy control, high processing speed, and a small standby current during standby.
FIG. 17
is a circuit diagram showing the configuration of a conventional CMOS SRAM memory cell.
Referring to
FIG. 17
, a conventional memory cell includes: an N-channel MOS transistor
580
which is connected between a bit line BL and a storage node N
100
and whose gate is connected to a word line WL; and an N-channel MOS transistor
582
which is connected between a bit line /BL and a storage node N
111
and whose gate is connected to the word line WL. The transistors each connecting a memory cell and a bit line are also called access transistors.
The conventional memory cell further includes: an N-channel MOS transistor
574
whose source is coupled to a ground potential GNDM of a memory cell array, whose drain is connected to the storage node N
100
, and whose gate is connected to the storage node N
111
; and an N-channel MOS transistor
578
whose source is coupled to the ground potential GNDM, whose drain is connected to the storage node N
111
, and whose gate is connected to the storage node N
100
. The transistors each for driving a storage node to the L level are also called driver transistors.
The conventional memory cell further includes: a P-channel MOS transistor
572
whose source is coupled to a power supply potential VCCM for the memory cell array, whose drain is connected to the storage node N
100
, and whose gate is connected to the storage node N
111
; and a P-channel MOS transistor
576
whose source is connected to the power supply potential VCCM, whose drain is connected to the storage node N
111
, and whose gate is connected to the storage node N
100
. The transistors each for bringing a storage node up to the H level are also called load transistors. A load transistor may be replaced by a high-resistance element.
FIG. 18
is a diagram showing an example where a small short circuit occurs between a storage node in the CMOS SRAM memory cell illustrated in FIG.
17
and the power source potential VCCM.
Referring to
FIG. 18
, the storage node N
111
in the memory cell is connected to the node to which the power supply potential VCCM is applied via a resistor R
11
having a high resistance value. Such a failure can be caused by a foreign matter such as a dust in a fabricating process, an unsatisfied etching condition, and the like.
As shown in
FIG. 18
, when the storage node N
111
as the drain of the P-channel MOS transistor
576
and also as the drain of the N-channel MOS transistor
578
holds the “L” level, a through current flows from the power supply potential VCCM to the ground potential GNDM in the path indicated by the arrow. Since the current continuously flows also in a standby state, a standby failure occurs in the semiconductor memory device.
The standby failure denotes a failure which occurs when a consumption current of the SRAM at the time of standby in a state where data is not accessed from the outside is larger than a specified value.
In the case where the resistance value of the resistor R
11
is sufficiently larger than resistance when the N-channel MOS transistor
578
is conducting, however, no particular influence is exerted on the function of reading/writing data from/to the SRAM. That is, no particular influence is exerted on the function and only a phenomenon that the standby current increases occurs. In such a case, there are problems such that a memory cell in which the standby current increases cannot be specified, so that even if the SRAM has a redundant circuit for replacement, the failure cannot be repaired.
FIG. 19
is a diagram showing an example where a small short circuit occurs between the storage node in the CMOS SRAM memory cell illustrated in FIG.
17
and the ground potential GNDM.
Referring to
FIG. 19
, the storage node N
100
is coupled to the ground potential GNDM via a resistor R
11
a
having a high resistance value. In a manner similar to the case of
FIG. 18
, such a failure can happen due to a foreign matter such as a dust in a fabricating process, an unsatisfied etching condition, and the like. When the storage node N
100
holds the “H” level and the storage node N
111
holds the “L” level, a small amount of a leak current flows from the storage node N
100
via the resistor R
11
a
to a node to which the ground potential GNDM is applied.
Since the current continuously flows also in the standby state, a standby failure occurs in the semiconductor memory device.
In the case where the resistance R
11
a
is sufficiently larger than resistance when the P-channel MOS transistor
572
as a load transistor is conducting, an influence is not particularly exerted on the operating function of the chip. That is, only the phenomenon that the standby current increases in the semiconductor memory device can be found from the outside. In such a case as well, there is a problem such that the memory cell in which the standby current increases cannot be specified and a repair cannot be made even if the chip has a redundant circuit.
FIG. 20
is a schematic diagram showing arrangement of circuit blocks of a conventional semiconductor memory device and arrangement of pads for receiving power supply potentials and pads for receiving ground potentials.
Referring to
FIG. 20
, a memory cell array
640
is disposed in the center portion of a chip
632
. Peripheral circuits
642
and
644
are disposed on both sides of the memory cell array
640
. In proximity to the middle point of one of long sides of the chip
632
, a pad
634
for supplying a power supply potential VCC to the peripheral circuits
642
and
644
and a pad
636
for supplying a power supply potential VCCM are disposed. The pad
634
and the peripheral circuits
642
and
644
are connected via a power supply line
652
. The pad
636
and the memory cell array
640
are connected via a power supply line
654
.
In proximity to the middle point of the other long side of the chip
632
, a pad
646
for supplying a ground potential GND to the peripheral circuits
642
and
644
and a pad
648
for supplying a ground potential GNDM to the memory cell array
640
are disposed. The pad
646
and the peripheral circuits
642
and
644
are connected via a power supply line
658
. The pad
648
and the memory cell array
640
are connected via a power supply line
660
.
In the conventional technique as well, as shown in
FIG. 20
, by providing the power supply potentials for the memory cell array and the peripheral circuits and the ground potentials for the memory cell array and the peripheral circuits so as to be isolated from each other, for example, whether a standby current failure is caused by the peripheral circuits or the memory cell can be determined. By making such determination, the semiconductor process can be improved.
In the case where the cause of the standby current failure is, for example, a memory cell, however, in the conventional configuration, it is difficult to specify a defective memory cell as the cause of the failure. The chip cannot be therefore repaired by replacing the defective memory cell by using the redundant circuit. Although inventions intended to repair the standby current failure and the like, such as the invention of semiconductor memory device and method of detecting DC current failure in memory cell described in Japanese Patent Laying-Open No. 8-45299 and the invention of semiconductor memory device described in Japanese Patent Laying-Open No. 8-138399 have been made, an invention teaching a method of specifying and repailing a defective memory cell has not been achieved.
SUMMARY OF THE INVENTION
An object of the present invention is t

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