Semiconductor memory device capable of reducing power...

Details Semiconductor memory device capable of reducing power... Semiconductor memory device capable of reducing power...

2006-02-14

2006-02-14

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Powering

Conservation of power

C365S205000, C365S154000

Reexamination Certificate

active

06999371

ABSTRACT:
The input data at address0is “00000000”, including many “0”s. The data at address0is inverted to “11111111”. At the same time, flag information “1” indicative of inversion is written into the flag bit of the same address0. The input data at address3also includes many “0”s. Therefore, the data of address3is inverted, and flag information “1” is written. The input data at addresses1and2includes more “1”s than “0”s. Therefore, the data is not inverted, and flag information “0” is written. With regards to the written data, only the data at an address whose flag signal is “1” is inverted again in a reading mode to be eventually read out as a data output signal.

REFERENCES:
patent: 5053998 (1991-10-01), Kannan et al.
patent: 5715191 (1998-02-01), Yamauchi et al.
patent: 9-274796 (1997-10-01), None
patent: 11-120760 (1999-04-01), None
patent: 2002-366419 (2002-12-01), None

Affiliated with

Also associated with

Rating

Semiconductor memory device capable of reducing power... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device capable of reducing power..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device capable of reducing power... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3694092