Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1993-10-27
1996-10-15
Lane, Jack A.
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
36518912, 365221, 36523005, 36523008, 36523009, 365236, 365239, 365240, G11C 804
Patent
active
055661246
ABSTRACT:
An improved video RAM (1) is disclosed which is capable of reading at a high speed a data signal necessary for image processing. The data signal stored in a row of memory cells designated by a row decoder (13) is held in a serial register (4). A mode decoder (8) is responsive to externally provided interval data to control a counter (7) such that the counter (7) generates internal addresses SY0 to SY7 incrementing at the designated intervals. A serial decoder (6) is responsive to the internal addresses SY0 to SY7 to designate the serial register (4) at the designated intervals. Accordingly, only required data is provided from the serial register (4), with the result that desired data can be provided in a short period of time.
REFERENCES:
patent: 4633441 (1986-12-01), Ishimoto
patent: 4667313 (1987-05-01), Pinkham et al.
patent: 4727481 (1988-02-01), Aguille et al.
patent: 4757473 (1988-07-01), Kurihara et al.
Fudeyasu Yoshio
Ito Junko
Lane Jack A.
Mitsubishi Denki & Kabushiki Kaisha
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