Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including high voltage or high power devices isolated from...
Reexamination Certificate
1998-07-16
2002-01-08
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including high voltage or high power devices isolated from...
C257S544000, C257S659000
Reexamination Certificate
active
06337506
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a dynamic random access memory (a DRAM).
2. Description of the Background Art
In a conventional DRAM, a peripheral circuit is arranged to divide a memory cell array into several regions.
FIG. 19
is a diagram showing a circuit arrangement of a conventional DRAM
300
.
Referring to
FIG. 19
, the conventional DRAM
300
includes: memory arrays
302
,
304
,
306
and
308
arranged in two rows and two columns; power supply circuits
326
and
328
and a control circuit
330
arranged between memory arrays
302
,
306
and
304
,
308
; pads PD
11
arranged between memory arrays
302
and
306
; and pads PD
12
arranged between memory arrays
304
and
308
.
Memory array
302
includes memory cell arrays
318
,
320
,
322
and
324
and array circuits
310
,
312
,
314
and
316
.
In the circuit arrangement shown in
FIG. 19
, there is a variation in the distances between the peripheral circuit and the array circuits. While a portion F of the array circuit is close to control circuit
330
, a portion E of the array circuit is spaced by a significant distance from control circuit
330
. Thus, the timing for every control signal must be set in consideration of the delay resulting between the peripheral circuit and portion E of the array circuit, which is spaced by the longest distance from the peripheral circuit.
On the other hand, in Japanese Patent Laying-Open No. 9-74171, a circuit arrangement has been disclosed in which a peripheral circuit is arranged in the central portion of a memory array so as to eliminate variation in signal delays between the peripheral circuit and the array circuits.
FIG. 20
is a schematic diagram shown in conjunction with the circuit arrangement of a conventional DRAM
342
which has been disclosed in the aforementioned laid open application.
Referring to
FIG. 20
, DRAM
342
includes four unit blocks
344
,
346
,
348
and
350
arranged in two rows and two columns.
Each of unit blocks
344
,
346
,
348
and
350
includes eight memory arrays and a peripheral circuit for the memory arrays. More specifically, unit block
344
includes: memory arrays M
11
, M
12
and M
13
arranged in the first row; memory arrays M
21
and M
23
arranged in the second row excluding the area in the second column; memory arrays M
31
, M
32
and M
33
arranged in the third row; and a peripheral circuit C
1
arranged in the second row of the second column.
As each of unit blocks
346
,
348
and
350
has an arrangement similar to that of unit block
344
, the description thereof will not be repeated here.
In conventional DRAM
300
shown in
FIG. 19
, the peripheral circuits (specifically, a control circuit, or a circuit such as a power supply circuit including a charge pump circuit or a ring oscillator) or the like, which are generation sources of electric charges, are distributed over the entire area of the chip. Therefore, electric charges are disadvantageously implanted into the adjacent memory cell through a substrate, resulting in a memory cell which cannot hold data well.
To cope with this problem, a common practice is to provide a guard ring between a peripheral circuit and a memory cell to prevent implantation of electric charges into the memory cell.
FIG. 21
is a diagram showing an arrangement of guard rings in a conventional semiconductor memory device.
Referring to
FIG. 21
, guard rings
368
and
370
are provided between a peripheral circuit
362
and a memory cell
364
and between peripheral circuit
362
and a memory cell
366
, respectively.
FIG. 22
is a diagram showing a cross section taken along the chain-dotted line G-G′ for the guard rings in FIG.
21
.
Referring to
FIG. 22
, electric charges
372
generated in peripheral circuit
362
are distributed into a P substrate
374
. The distributed electric charges
372
are captured by guard rings
368
and
370
before reaching the memory cell provided adjacent to power supply circuit
362
.
In the conventional DRAM, an extra layout area is required to provide the guard rings.
In addition, due to a high frequency signal generated by a ring oscillator, noise may be introduced to an analog circuit within the same chip and transmitted to other semiconductor devices in the same equipment (especially in the same printed circuit board).
FIG. 23
is a circuit diagram showing an oscillator used in a conventional semiconductor memory device.
The ring oscillator includes an NAND circuit
382
receiving a control signal Rin; four inverters
384
,
386
,
388
and
390
connected in series and receiving an output from NAND circuit
382
; and three inverters
392
,
394
and
396
connected in series and receiving, inverting and amplifying an output from inverter
390
.
An output from inverter
390
is fed back to an input to NAND circuit
382
.
FIG. 24
is a diagram showing a circuit arrangement of the ring oscillator shown in FIG.
23
.
Referring to
FIGS. 23 and 24
, NAND circuit
382
includes P channel MOS transistors
382
p
1
and
382
p
2
and N channel MOS transistors
382
n
1
and
382
n
2
.
Inverter
384
includes a P channel MOS transistor
384
p and an N channel MOS transistor
384
n. Inverter
386
includes a P channel MOS transistor
386
p and an N channel MOS transistor
386
n.
Inverter
388
includes a P channel MOS transistor
388
p and an N channel MOS transistor
388
n.
Inverter
390
includes a P channel MOS transistor
390
p and an N channel MOS transistor
390
n.
Inverter
392
includes a P channel MOS transistor
392
p and an N channel MOS transistor
392
n.
Inverter
394
includes a P channel MOS transistor
394
p and an N channel MOS transistor
394
n.
Inverter
396
includes a P channel MOS transistor
396
p and an N channel MOS transistor
396
n.
The P channel MOS transistors included in the ring oscillator are covered with a second metal interconnection
402
for supplying a power supply potential. The N channel MOS transistors included in the ring oscillator are covered with a second metal interconnection
404
for supplying a ground potential.
For inverter
384
, second metal interconnection
402
for supplying the power supply potential is connected to a first metal wiring
414
at a via hole
406
. First metal wiring
414
is connected to a source
384
ps of P channel MOS transistor
384
at a contact hole
410
.
Second metal interconnection
404
for supplying the ground potential is connected to a first metal wiring
416
at a via hole
408
. First metal wiring
416
is connected to a source
384
ns of N channel MOS transistor
384
n at a contact hole
412
.
P channel MOS transistor
384
p and N channel MOS transistor
384
n have their drains
384
pd and
384
nd connected to a first metal wiring
424
at contact holes
426
and
428
, respectively. A first metal wiring
418
, to which the output from NAND circuit
382
is applied, is connected to gates
384
pg and
384
ng of P channel MOS transistor
384
p and N channel MOS transistor
384
n at contact holes
420
and
422
.
Similarly, a first metal wring
424
, to which the output from inverter
384
is applied, is connected to gates of P channel MOS transistor
386
p and N channel MOS transistor
386
n at contact holes.
Thus, an output from inverter
386
is connected to an input to inverter
388
, and an output from inverter
388
is connected to an input to inverter
390
.
FIG. 25
is a schematic diagram showing a cross section taken along the chain-dotted line X-X′ in FIG.
24
.
Referring to
FIG. 25
, a P well
454
is formed on a P substrate
452
, and an N channel MOS transistor
384
n is formed in P well
454
. N channel MOS transistor
384
n has its source
456
and drain
458
connected to first metal wirings
416
and
424
at contact holes.
Thereabove, second metal interconnection
404
is formed to cover the ring oscillator through an insulation layer. A protection film
464
is formed on second metal interconnection
404
.
The ring oscillator is generally c
Amano Teruhiko
Arimoto Kazutami
Fujino Takeshi
Kinoshita Mitsuya
Kobayashi Mako
McDermott & Will & Emery
Prenty Mark V.
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