Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means
Reexamination Certificate
2000-01-05
2002-10-15
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular power supply distribution means
C257S202000, C365S051000, C365S063000
Reexamination Certificate
active
06465818
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor memory device wherein a memory cell array is divided into banks to write and read data in parallel.
2. Description of Related Background Art
Conventionally, there are various electronic systems comprising various built-in memory devices. For example, there is an electronic system wherein an EEPROM flash memory and an SRAM are built in, and data of the flash memory are stored in the SRAM to be exchanged between a CPU and the flash memory via the SRAM and to be directly rewritable without the need of the SRAM.
On the other hand, in recent years, there is known a memory system called a dual operation type (or a dual port type) memory system which is capable of reading data from a certain memory area while writing data in another memory area in order to reduce the number of memory chips necessary for the memory system. In order to construct a memory system of this type, two completely independent memory areas may be simply provided in a memory device.
However, if independently accessed memory areas are simply provided in the memory device, there are still many problems as a dual operation type memory system. First, since a decoder and a sense amplifier must be provided independently in each of the memory areas, the layout area of the memory system is large. Secondly, if bit lines and word lines are continuously provided independently in each of the memory areas, it is not possible to divide each of the memory areas into blocks to read and write data every block. That is, the memory areas for reading and writing data in parallel are fixed. However, in fact, with respect to the capacities of the memory areas capable of reading and writing data in parallel, there are various requests in accordance with the use of the memory device and so forth. In order to apply the memory device to various uses, various memory areas having different capacities must be prepared.
On the other hand, an EEPROM flash memory capable of optionally dividing a single memory cell array area into blocks to write and read data in parallel every block is proposed in, e.g., Japanese Patent Laid-Open No. 10-144086. In this memory, a memory cell array is divided into a plurality of blocks along a line perpendicular to word lines, and a separating transistor is inserted into each of the word lines between adjacent blocks, so that the size of memory areas for the dual operation can variably set by the ON-OFF control of the separating transistor.
However, in the above described dual operation type flash memory, there are still the following problems, since the memory cell array area is divided into blocks along the line perpendicular to the word lines. First, a high voltage boosted during a data writing operation is used for the word lines. Therefore, for example, when data are written by selectively driving the word lines of an intermediate block using a left row decoder, the word lines are common to an unselected block adjacent to the left side of a selected block, so that the unselected block is in a half-write state. Therefore, the deterioration of data in the unselected block increases, and erroneous write and so forth are easily caused. Secondly, row decoder circuits having the same structure must be provided on both sides of the memory cell array in the directions of the word lines, so that the layout area of the memory system is large.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a semiconductor memory device of a dual operation type, which divides a memory cell array into banks by separating bit lines, and of a semi-custom system capable of easily changing of the capacities of the banks.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor memory device comprising: a memory cell array having a plurality of memory cells, each of which is arranged at a corresponding one of intersections, at which bit lines intersect word lines, the memory cell array being divided into first and second banks along a line intersecting the bit lines, which are separated between the first and second banks; a first sense amplifier arranged on one side of the directions of the bit lines of the memory cell array, the first sense amplifier being connected to the bit lines of the first bank to sense signals of the bit lines of the first bank; a second sense amplifier arranged on the other side of the directions of the bit lines of the memory cell array, the second sense amplifier being connected to the bit lines of the second bank to sense signals of the bit lines of the second bank; a row decoder for selectively driving the word lines of the memory cell array; and a parallel control circuit for allowing one of the first and second banks to perform a data writing or erasing operation while allowing the other of the first and second banks to perform a data reading operation.
According to the present invention, the sense amplifier circuits are arranged on both end portions of the memory cell array, and the division of the memory cell array into banks is carried out by separating the bit lines along the line intersecting the bit lines. Even if the division of the memory cell array into banks along the line intersecting the bit lines is carried out, if the sense amplifier circuits of the divided banks are arranged between the banks, it is required to greatly change the chip layout in accordance with the change of the layout of the sense amplifier circuits in order to change the capacities of the banks. On the other hand, according to the present invention, since the sense amplifier circuit are arranged on both sides of the memory cell array, it is not required to change the layout of the memory cell array and the sense amplifier circuits when the capacities of the banks are changed, and it has only to change a process for patterning a wiring layer or the like constituting the bit lines. That is, if a master chip before a wiring process is prepared, various products having different capacity ratios of divided banks at a user's request can be simply produced by only the design change of wiring. Thus, the turn-around-time (TAT) of a dual operation type memory device can be shortened.
Furthermore, the architecture of the row decoder part for selectively driving the word lines must also be changed due to the division into banks using separating the bit lines. This can be simply changed by separating address signal lines at a place corresponding to the separated place of the bit lines, if the number of address signal lines arranged on one end side of the memory cell array in the directions of the word lines is previously prepared so as to be able to cope with the change of the division into banks. However, also in this case, as described above, the number of the address signal lines capable of covering the whole variable range of the capacities of the divided banks must be previously prepared, and a pre-decoder must be prepared so as to be able to simultaneously drive the divided address signal lines. However, even if these arrangements must be made, the increase of the layout area is smaller than that when row decoders having the same architecture are arranged on both sides of the word lines in order to divide the memory cell array into banks along the line perpendicular to the word lines.
Alternatively, according to the present invention, at least two separating transistors may be provided in the bit lines of the memory cell array, and a separation control circuit including a non-volatile memory, such as a fuse circuit, for controlling ON-OFF of the separating transistors may be provided, so that the division of the memory cell array into banks may be carried out by the programming of the separation control circuit. Also in this case, it is possible to simply divide the memory cell array into banks after a memory chip is completed, so that the TAT can be shortened.
The
Dickey Thomas L
Hogan & Hartson LLP
Kabushiki Kaisha Toshiba
Tran Minh Loan
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