Semiconductor memory device capable of operating at high speed

Details Semiconductor memory device capable of operating at high speed Semiconductor memory device capable of operating at high speed

2006-08-22

2006-08-22

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S063000, C365S233100

Reexamination Certificate

active

07095673

ABSTRACT:
A plurality of sub-arrays include a plurality of memory elements. First bit line pairs are connected to a plurality of memory elements provided in each of the sub-arrays. Second bit line pairs are provided so as to correspond to a plurality of sub-arrays. The first bit line pairs supply signals to the second bit line pairs. The second bit line pairs are operated at a lower frequency than the first bit line pairs.

REFERENCES:
patent: 5386394 (1995-01-01), Kawahara et al.
patent: 6517887 (2003-02-01), Lilieblad
patent: 6704828 (2004-03-01), Merritt et al.
patent: 10-308089 (1998-11-01), None
patent: 2002-100187 (2002-04-01), None
Steven K. Hsu, et al. “A 4.5 GHz 130nm 32KB LO Cache with a Self Reserve Bias Scheme”, 2002 Symposium on VLSI Circuits Digest of Technical Papers, pp. 48-49.

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