Semiconductor memory device capable of monitoring and...

Details Semiconductor memory device capable of monitoring and... Semiconductor memory device capable of monitoring and...

2000-08-04

2001-06-26

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S201000, C365S195000, C365S196000, C365S189030

Reexamination Certificate

active

06252820

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in Japanese Patent Application No. H11-222781 filed on Aug. 5, 1999 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates generally to a clock synchronous semiconductor memory device.
FIG. 10
shows the construction of a conventional clock synchronous SRAM. A memory cell array
101
has memory cells at the points of intersection between bit line pairs and word lines. A row decoder
105
a
and a word line driving circuit
105
b
are provided in order to selectively drive the word lines of the memory cell array
101
. A column decoder
106
and a column gate
109
are provided in order to select the bit lines.
An address Add is incorporated into an address buffer
104
to feed a row address RA and a column address CA to the row decoder
105
a
and the column decoder
106
, respectively. The address buffer
104
includes an address latch to control the incorporation of the address in synchronism with a clock signal CLK incorporated into a clock buffer
102
. The incorporation of a chip enable signal /CE (/ denotes negative logic) and a write enable signal /WE into a command buffer
107
is also controlled by the clock signal CLK. An output enable signal /OE is not synchronous-controlled.
The clock signal CLK incorporated into the clock buffer
102
is fed to a control signal generator circuit
103
for generating various control pulse signals synchronized with the clock signal CLK. Specifically, the control signal generator circuit
103
is designed to generate a sense amplifier pulse signal SAP for activating a sense amplifier
110
, a writing pulse signal WP for activating a writing circuit
111
, and a word line pulse signal WLP for activating a word line driving circuit
105
b.
The chip enable signal /CE and write enable signal /WE incorporated into the command buffer
107
, and the output enable signal /OE transferred to the command buffer
107
are logically synthesized in a command decoder
108
to generate a sense amplifier control signal SAC, which is associated with the sense amplifier pulse signal SAP for activating the sense amplifier circuit
110
, a writing circuit control signal WCC, which is associated with the writing pulse signal WP for activating the writing circuit
111
, and an output buffer control signal OBC for activating a reading data buffer
112
. Data incorporated into a written data buffer
113
are supplied to the memory cell array via the writing circuit
111
which is activated by the writing pulse signal WP and the writing circuit control signal WCC.
FIGS. 11A and 11B
are timing charts for explaining the operation of the clock synchronous SRAM of
FIG. 10
, and each of these figures shows a write cycle and a subsequent read cycle.
In the above described clock synchronous SRAM, it is required to optimally set the timing and pulse width of an internal control signal which is generated by the control signal generator circuit
103
. Specifically, the setting of the timing and pulse width of the internal control signal is as follows.
(a-1) In order to prevent an erroneous word line from being selected, it is required to set the timing of the generation of the word line pulse signal WLP after the output signal of the row decoder
105
a
is decided as shown in
FIGS. 11A and 11B
. However, if this timing is set late, the subsequent operation is delayed to lower the circuit operating speed.
(a-2) The pulse width of the word line pulse signal WLP determines a period of time, in which a word line is activated. The time required to activate the word line must be the time required to transfer memory cell data at a sufficient amplitude from a bit line to the sense amplifier
110
via a data line. However, if this time is too long, the electric current consumption of the memory cell increases.
(b-1) In order to prevent data from being written in a bit line of an erroneous column, it is required to set the timing of the generation of the writing pulse signal WP after the output signal of the column decoder
106
is decided as shown in FIG.
11
A. However, if this timing is set late, the subsequent operation is delayed to lower the circuit operating speed.
(b-2) The pulse width of the writing pulse signal WP determines the time required to activate the writing circuit
111
. The time required to activate the writing circuit
111
must be the time required to sufficiently transfer written data to the data line and bit line to invert the memory cell data. However, if this time is too long, the starting of the subsequent pre-charging of the bit line is delayed. As a result, if the operating frequency is high, written data also remain in the bit line during the next reading operation to have a bad influence on the data reading operation.
(c) It is required to set the timing of the generation of the sense amplifier pulse signal SAP so as to activate the sense amplifier
110
after the amplitude of data transferred to a data line sufficiently increases. If this timing is too early, there is a possibility that the sense amplifier
110
malfunctions, and if the timing is too late, the reading operating speed is lowered.
It is difficult to carry out the above described setting of the timing and pulse width of the internal control signal, since the influence of the parasitic capacity and parasitic resistance of signal lines increases with the scale down of patterns and the increase of memory capacities. In order to carry out the optimum setting, it is required to prepare a plurality of trial products having different numbers of stages of inverter chains for setting the timing to estimate the characteristics of these trial products. It is very expensive and takes a lot of time to estimate the trial products, so that the cost of producing the memory is high.
In addition, in order to surely prevent the malfunction of the circuit, it is required to set the timing and so forth at the sacrifice of the operating speed and electric current consumption. However, it is not conventionally possible to confirm whether excessive sacrifices are made for the operating speed and electric current consumption.
There is another problem in that the certification and estimation of the circuit operation can not be carried out by means of an inexpensive tester having a low operating frequency when the operating frequency of the memory becomes high. If the certification and estimation can not carried out unless an expensive tester operating at a high speed is used, the cost of producing the memory is high.
Specifically, FIGS.
12
(
a
) and
12
(
b
) show principal parts extracted from the operating timing charts shown in
FIGS. 11A and 11B
, when the operating frequencies are low and high, respectively.
When the word line pulse signal WLP and the write pulse signal WP fall to complete writing into a memory cell, a bit line pair is charged to VCC by means of a pre-charging circuit. However, the written data on the bit line have a much lower potential on the “L” side than the read data, so that it takes a lot of time to charge to VCC.
In the case of
FIG. 12A
, since the cycle time is long, the written data on the bit line does not exist when the word line is activated in the subsequent read cycle, so that the sense amplifier pulse signal SAP is generated after the bit line pair is sufficiently pre-charged to VCC and read data sufficiently appears on the bit line. In this case, the data reading operation using the sense amplifier circuit is not disturbed by the written data in the last cycle.
However, if the cycle time is shortened as shown in
FIG. 12B
, the time assigned to pre-charge the bit line is shortened, so that the sense amplifier pulse signal SAP is generated before the bit line is sufficiently charged to VCC. Therefore, when the read data in the read cycle is opposite to the last written data, since the read data does not sufficiently appear on the bit l

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