Semiconductor memory device capable of increasing writing speed

Details Semiconductor memory device capable of increasing writing speed Semiconductor memory device capable of increasing writing speed

2011-04-26

2011-04-26

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185240, C365S185170, C365S230060

Reexamination Certificate

active

07933152

ABSTRACT:
A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage≧the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation.

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Japanese Office Action (with English translation) issued on Feb. 1, 2011, in Japanese Patent Application No. 2005-205950 (5 pages).

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