Semiconductor memory device capable of improving read...

Details Semiconductor memory device capable of improving read... Semiconductor memory device capable of improving read...

2000-04-11

2001-04-17

Nelms, David (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S230030, C365S207000

Reexamination Certificate

active

06219269

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to an improvement of the read operation speed of a dynamic random access memory (DRAM) device.
2. Description of the Related Art
In a prior art semiconductor memory device including a plurality of sense amplifiers arranged in rows, columns, a plurality of local data input/output line pairs, each pair being connected to one row of the sense amplifiers, a global data input/output line pair, and a plurality of switches each connected between one of the local data input/output line pairs and the global data input/output line pair, a pull-up circuit and a differential amplifier are connected to the global data input/output line pair. In this case, the pull-up circuit is provided near the differential amplifier. This will be explained later in detail.
In the above-described prior art semiconductor memory device, however, the pull-up circuit is provided near the differential amplifier, the amount of signals supplied to the differential amplifier is so small that the read operation speed is decreased. This also will be explained later in detail.
SUMMARY OF THE INVENTION
It is an object of the present invention to improve the read operation speed of a semiconductor memory device.
According to the present invention, in a semiconductor memory device including a plurality of sense amplifiers arranged in rows, columns, a plurality of local data input/output line pairs, each pair being connected to one row of the sense amplifiers, a global data input/output line pair, a plurality of switches each connected between one of the local data input/output line pairs and the global data input/output line pair, and a differential amplifier connected to the global data input/output line pair, at least one pull-up circuit is connected to the global data input/output line pair. At least one of the switches is connected to the global data input/output line pair between the pull-up circuit and the differential amplifier. For example, the pull-up circuit is provided at an intermediate portion of the global data input/output line pair.
Also, in a semiconductor memory device including a plurality of sense amplifiers arranged in rows, columns, a plurality of local data input/output line pairs, each pair being connected to one row of the sense amplifiers, a global data input/output line pair, a plurality of switches each connected between one of the local data input/output line pairs and the global data input/output line pair, and a differential amplifier connected to the global data input/output line pair, one pull-up circuit is connected to each of the local data input/output line pairs.


REFERENCES:
patent: 5943253 (1999-08-01), Matsumiya et al.
patent: 5-120876 (1993-05-01), None
patent: 6-20465 (1994-01-01), None
patent: 9-27190 (1997-01-01), None

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