Semiconductor memory device capable of data transfer between mem

Details Semiconductor memory device capable of data transfer between mem Semiconductor memory device capable of data transfer between mem

1994-07-29

1996-10-15

Swann, Tod R.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523005, 36523009, 365220, 365281, 36518905, 365174, 365219, G11C 800

Patent

active

055663710

ABSTRACT:
A dual port random access memory capable of inputting/outputting data bit by bit includes a plurality of memory cell arrays (100a, 100b, 100c, 100d) accessible in parallel, a plurality of data registers (9a, 9b, 9c, 9d) arranged to be connected to memory arrays, and transfer gates (8a', 8b', 8c', 8d') for selectively connecting each of the data registers to one memory array in response to a destination designating signal. The transfer gate includes elements (T1, T2) for connecting the data registers and the memory arrays such that each of the plurality of memory arrays is connected to different data registers. Each of the data registers is capable of transferring data of one row of the memory array at one time. The data register is capable of serially inputting and outputting data. This structure enables rearrangement of data and transfer of data row by row between memory arrays in the memory device.

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