Static information storage and retrieval – Addressing
Reexamination Certificate
2001-12-04
2004-09-14
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
C365S230060, C365S189050
Reexamination Certificate
active
06791896
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device capable of internally changing the address space structure.
2. Description of the Background Art
A semiconductor memory device has been widely used because of its small size for large storage capacity, and of short access time. In such a semiconductor memory device, the size of the address space is determined by the number of bits of an address signal applied to address input pin terminals, and a storage capacity accommodating to the address space is selected according to each application. The storage capacity is determined by the size of the address space and the number of bits of word configuration.
In such a semiconductor memory device, the number of bits of the data to be processed (i.e., word configuration) is different depending on applications. Therefore, semiconductor memory devices having the same internal configuration but different word configurations such as ×1-bit, ×4-bit, and ×8-bit configurations are manufactured, and selected in terms of the word configuration according to each application.
In general, manufacturing the semiconductor memory devices of different word configurations according to different design specifications degrades the design efficiency and also increases the number of types of semiconductor memory devices, thereby complicating the product management. Therefore, the semiconductor memory devices are configured so as to accommodate to different word configurations with the same chip structure. When a common chip structure is used for a plurality of word configurations, a common internal structure is used for the plurality of word configurations. A required word configuration is implemented by fixing a potential of a specific pad using a mask interconnection or a bonding wire.
In the case of a semiconductor memory device requiring a refresh operation such as a DRAM (Dynamic Random Access Memory), semiconductor memory devices having different refresh cycles are manufactured with the same internal structure and the refresh cycle is determined according to a factor such as power consumption of the whole system or the like. As in the case of the word configuration, a required refresh cycle is determined by a mask interconnection or a bonding option (fixing of a pad potential by the bonding wire).
The word configuration is normally changed by degenerating an internal column address signal bit so as to increase the number of data bits. The refresh cycle is changed by, e.g., degenerating a row address signal bit, or internally exchanging a prescribed row address signal bit with a prescribed column address signal bit.
In the pad option as described above, the internal structure is the same, and the number of internal circuits (e.g., input/output circuits) to be simultaneously activated is changed according to the word configuration, thereby accommodating to a plurality of different specifications (e.g., word configurations and refresh cycles). However, the address space to be used in these semiconductor memory devices is the entire address space corresponding to the storage capacity of the memory array thereof. For example, a 1-M bit semiconductor memory device uses a 20-bit address signal in the case of the configuration of 1 M words ×1 bit, but uses an 18-bit address signal in the case of the configuration of 256 K words ×4 bits. In the case where a memory system of 1 M words ×4 bits is to be configured with these semiconductor memory devices, four semiconductor memory devices of which type are used is determined according to the applied system conditions such as current consumption and system size.
However, the minimum address space has been inherently determined by the storage capacity and word configuration of a single semiconductor memory device. For example, in the case of using a semiconductor memory device of 256 Kbits ×4 bits, the number of addresses of the memory system is at least 2
18
. In a small-scale processing system, a semiconductor memory device having an address space suitable for the application is employed so as not to unnecessarily increase the address space of the memory system. This necessitates manufacturing of many kinds of semiconductor memory devices having the same word configuration but different address space sizes. However, designing such semiconductor memory devices according to the respective specifications degrades the design efficiency, and also requires management of many kinds of products, resulting in complicated product management, as in the case of the word configurations and refresh cycles described above.
Moreover, in the case where the number of kinds of address space sizes of the semiconductor memory devices is increased, the number of address signal bits is also various for accommodating to a different address space size. Therefore, a test program must be prepared for each type of semiconductor memory device, resulting in increased costs of the semiconductor memory devices.
In this case, it may be possible to externally fix the voltage on an address signal input pin terminal so as to fix the address space to be used. However, in the case of the DRAM, row and column address signals are applied to common pin terminals in a time division multiplexed manner. Therefore, it is impossible to fix the voltage on a specific address signal input pin terminal upon assembling into a system. Moreover, depending on the size of the address space to be used, it may not be possible to maintain compatibility with another type of semiconductor memory device having a different configuration of the row and column address signal bits.
Especially, in recent years, a plurality of semiconductor memory devices are packaged in a single module to increase the number of data bits, in order to improve the data transfer rate. In such a memory module, the number of semiconductor memory devices to be packaged is fixed by the module package. From the standpoint of the number of kinds of products, the commonization of address space size is a more significant issue to be considered than conversion of the word configuration.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device capable of coping with a plurality of address space sizes.
It is another object of the present invention to provide a semiconductor memory device capable of easily implementing a memory module having address spaces of different sizes.
A semiconductor memory device according to the present invention includes: a memory array having an address space of a prescribed size; and an address setting circuit for changing the size of the address space according to an address mode designation signal while maintaining a word configuration of the address space.
According to the present invention, the size of the address space is changed according to the address mode designation signal using the address setting circuit in the semiconductor memory device. Thus, semiconductor memory devices implementing a plurality of types of address spaces can be provided with a semiconductor memory device having a single internal structure. By packaging this semiconductor memory device into a module, a memory module having a plurality of types of address spaces can be implemented with a single type of semiconductor memory devices.
Converting a specific row address signal bit into an internal column address signal bit makes it possible to easily cope even with the case where external row and column address configurations are different depending on the address space size.
When this semiconductor memory device and a plurality of other types of semiconductor memory devices are packaged in a single module, the size of the address space of the semiconductor memory device of the invention is changed according to the address mode designation signal, to accommodate the number of bits of the address signal to t
Fudeyasu Yoshio
Ishida Kozo
Tsuruda Tamaki
Elms Richard
McDermott & Will & Emery
Nguyen Nam
Renesas Technology Corp.
LandOfFree
Semiconductor memory device capable of changing an address... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device capable of changing an address..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device capable of changing an address... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3257154