Semiconductor memory device capable of adjusting phase of...

Details Semiconductor memory device capable of adjusting phase of... Semiconductor memory device capable of adjusting phase of...

2001-10-11

2003-05-27

Tran, M. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

06570815

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a system on which the semiconductor memory device is mounted. More particularly, the invention relates to a semiconductor memory device for outputting data synchronously with a clock signal and a system on which the semiconductor memory device is mounted.
2. Description of the Background Art
In recent years, in order to transfer/receive data at high speed, a double data rate synchronous dynamic random access memory (DDR SDRAM) capable of outputting data synchronously with both rising and falling edges of a clock signal is used.
On a system using this memory, in many cases, a plurality of DDR SDRAMs and a controller for transmitting/receiving data to/from the DDR SDRAMs are mounted.
In such a memory system, external clock signals of the same phase are input to the controller and the DDR SDRAMs. The DDR SDRAM is designed so that a data output signal DQ is switched at the phase of the rising edge and that of the falling edge of an external clock signal supplied.
FIG. 14
is a block diagram showing the configuration of a conventional DDR SDRAM
501
.
Referring to
FIG. 14
, DDR SDRAM
501
includes an address buffer
504
for receiving external address signals A
0
to A
11
and bank address signals BA
0
and BA
1
and generating internal address signals INTA
0
to INTA
11
; a clock signal buffer
502
for receiving external clock signals CLK and /CLK and a clock enable signal CKE and generating an internal clock signal ICLK; a control signal buffer
506
for receiving a chip select signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE, and input/output DQ mask signals UDM and LDM synchronously with internal clock signal ICLK; a control circuit
508
for receiving internal clock signal ICLK, internal address signals INTA
0
to INTA
11
and an output of control signal buffer
506
and controlling the whole chip; and a mode register
510
for holding an operation mode of the SDRAM according to an output of the control signal buffer in response to an instruction of control circuit
508
.
DDR SDRAM
501
further includes: a DQ buffer
514
for transmitting/receiving a data signal to/from an external data bus; and memory arrays
512
a
to
512
d
for holding data input from the outside. Memory arrays
512
a
to
512
d
are four banks which can operate independent of each other.
DDR SDRAM
501
further includes: a DLL (Delay Locked Loop) circuit
516
for receiving internal clock signal ICLK as a clock signal BUFFCLK from clock signal buffer
502
and outputting a clock signal CLKP to DQ buffer
514
; and a QFC and QS buffer
518
for outputting control signals /QFC, UDQS, and LDQS in accordance with control timings of DQ buffer
514
.
Control signal /QFC can be used as a control signal for isolating the external bus from other devices when a read or write access is made to DDR SDRAM. Control signals UDQS and LDQS are strobe signals used by a controller to capture a data signal outputted to the external data bus.
FIG. 15
is a diagram for explaining the configuration of mode register
510
and control circuit
508
in FIG.
14
.
Referring to
FIG. 15
, the control circuit
508
includes a command decoder
622
for receiving and decoding an output of control signal buffer
506
to detect a command and, when a mode register set command is detected, activating a control signal /MSET to the L level; an inverter
624
for receiving and inverting control signal /MSET and outputting a control signal MSET; and clocked inverters
650
to
652
which are made active in association with activation of the control signal MSET, and receive and invert internal address signals INTA
0
to INTA
2
, respectively, from address buffer
504
.
For simplicity of explanation, the configuration of control circuit
508
only with respect to the portion of writing data to mode register
510
is shown.
Mode register
510
includes latch circuits
630
to
632
for receiving outputs of clocked inverters
650
to
652
, respectively, and inverters
640
to
642
for receiving and inverting outputs of latch circuits
630
to
632
and outputting signals K
0
to K
2
, respectively.
Latch circuit
630
includes an inverter
662
for receiving and inverting an output of clocked inverter
650
, and an inverter
660
for receiving and inverting an output of inverter
662
and feeding back the resultant to the input of inverter
662
. Since the configuration of each of latch circuits
631
and
632
is similar to that of latch circuit
630
, its description will not be repeated.
FIG. 16
is a circuit diagram showing the configuration of DLL circuit
516
in FIG.
14
.
Referring to
FIG. 16
, DLL circuit
516
includes: a delay line
32
for delaying clock signal BUFFCLK and outputting a clock signal CLKP; a replica buffer
34
for receiving clock signal CLKP, compensating delay time of DQ buffer
514
in
FIG. 14
as an output buffer, and outputting a clock signal FBCLK; and a phase comparator
38
for comparing the phase of clock signal BUFFCLK and that of clock signal FBCLK and outputting control signals a[
0
] to a[
2
].
Delay line
32
receives clock signal BUFFCLK by its node N
1
. Delay line
32
includes: an N-channel MOS transistor
44
connected between nodes N
1
and N
2
and for receiving control signal a[
0
] by its gate; a delay circuit
56
whose input is connected to node N
2
and whose output is connected to a node N
3
; and a P-channel MOS transistor
46
connected between nodes N
1
and N
3
and for receiving control signal a[
0
] by its gate.
Delay line
32
further includes: an N-channel MOS transistor
48
connected between nodes N
3
and N
4
and for receiving control signal a[
1
] by its gate; a delay circuit
58
whose input is connected to node N
4
and whose output is connected to a node N
5
; and a P-channel MOS transistor
50
connected between nodes N
3
and N
5
and for receiving control signal a[
1
] by its gate.
Delay line
32
further includes: an N-channel MOS transistor
52
connected between nodes N
5
and N
6
and for receiving control signal a[
2
] by its gate; a delay circuit
60
whose input is connected to node N
6
and whose output is connected to a node N
7
; and a P-channel MOS transistor
54
connected between nodes N
5
and N
7
and for receiving control signal a[
2
] by its gate.
Delay circuit
56
includes two inverters connected in series. Delay circuit
58
includes four inverters connected in series. Delay circuit
60
includes eight inverters connected in series.
Replica buffer
34
includes inverters connected in series having delay time corresponding to delay time of DQ buffer
514
.
FIGS. 17 and 18
are operational waveform charts for explaining the operation of DLL circuit
516
shown in FIG.
16
.
First, by referring to
FIGS. 16 and 17
, clock signal BUFFCLK goes high at time t
1
and, in response to this, clock signal CLKP goes high at time t
2
after the delay time of delay line
32
.
At time t
3
after the delay time of replica buffer
34
for compensating a delay in an output buffer since time t
2
, clock signal FBCLK goes high.
Phase comparator
38
compares the rising edge of clock signal FBCLK at time t
3
and that of clock signal BUFFCLK at time t
4
, and determines that the phase of clock signal FBCLK is advanced as compared with that of clock signal BUFFCLK.
Phase comparator
38
changes a control signal A[
2
:
0
] to increase delay time of delay line
32
.
Referring now to
FIGS. 16 and 18
, after the delay time of delay line
32
is increased, delay time during a period from rising time t
1
of clock signal BUFFCLK to rising time t
2
of clock signal CLKP increases. At time t
3
, the phase at the rising edge of clock signal BUFFCLK and that at the rising edge of clock signal FBCLK coincides with each other.
As described above, the conventional DDR SDRAM is designed so that the data DQ is switch

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