Semiconductor memory device capable of accurately writing data

Details Semiconductor memory device capable of accurately writing data Semiconductor memory device capable of accurately writing data

2002-11-27

2004-12-07

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189011

Reexamination Certificate

active

06829173

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices. In particular, the present invention relates to a semiconductor memory device including a plurality of memory cells each having two storage areas.
2. Description of the Background Art
NROM (Nitride Read-Only Memory) is now attracting attention as one of flash EEPROMs (Electrically Erasable Programmable Read-Only Memories) that are nonvolatile semiconductor memory devices. The NROM is disclosed in U.S. Pat. No. 6,011,725.
FIG. 22
is a circuit diagram showing a configuration of a memory cell array of a conventional semiconductor memory device.
Referring to
FIG. 22
, the memory cell array includes a plurality of nonvolatile memory cells MCs, a plurality of bit lines BLs and a plurality of word lines WLs.
Word lines WLs are arranged in respective rows and bit lines BLs are arranged in respective columns.
Nonvolatile memory cells MCs are arranged correspondingly to the crossings of word lines WLs and bit lines BLs. Nonvolatile memory cells MCs arranged in the same row are connected in series, having respective gates connected to the same word line WL. Bit lines BLs are each placed to pass the point where two nonvolatile memory cells MCs adjacent to each other are connected.
Nonvolatile memory cells MCs each have two storage areas L
1
and L
2
.
FIG. 23
shows a cross section of one of the nonvolatile memory cells shown in FIG.
22
.
Referring to
FIG. 23
, the nonvolatile memory cell includes a semiconductor substrate
1
, two diffusion bit lines (hereinafter referred to as diffusion layers)
7
A and
7
B, oxide films
8
and
10
, a nitride film
9
, and a control gate
21
.
Two diffusion layers
7
A and
7
B are formed with a predetermined distance therebetween on the main surface of semiconductor substrate
1
. Oxide film
8
is formed on semiconductor substrate
1
and between the two diffusion layers. Nitride film
9
is formed on oxide film
8
, oxide film
10
is formed on nitride film
9
, and control gate
21
is formed on oxide film
10
.
The nonvolatile memory cell can accumulate electrons in each of storage areas L
1
and L
2
in nitride film
9
. In other words, the NROM allows electrons to be accumulated in two physically different places within one cell to store 2-bit data per cell.
The electrons accumulated in storage areas L
1
and L
2
in nitride film
9
cannot move freely in nitride film
9
and thus stay in storage areas L
1
and L
2
, since nitride film
9
is an insulating film.
The semiconductor memory device as discussed above is easy to manufacture and the manufacturing cost is low. The memory cell array having the nonvolatile memory cell as shown in
FIG. 23
includes the diffusion bit lines and word lines orthogonal to each other as shown in FIG.
22
. Here, as memory cells adjacent to each other share the same diffusion bit line, the area of the memory cell array is reduced relative to that of conventional flash EEPROMs.
Description is now given below of data writing/reading operations into/from each of the storage areas L
1
and L
2
of the nonvolatile memory cell MC.
FIGS. 24-27
illustrate writing/reading operations of data for the two storage areas in the nonvolatile memory cell MC.
Referring to
FIG. 24
, nonvolatile memory cell MC has its gate connected to word line WL, and the memory cell MC is connected to bit lines BL
0
and BL
1
. Nonvolatile memory cell MC has its sides corresponding respectively to bit lines BL
0
and BL
1
, and storage area L
1
is placed on the side corresponding to bit line BL
0
as shown in
FIGS. 24 and 25
while storage area L
2
is placed on the side corresponding to bit line BL
1
as shown in
FIGS. 26 and 27
.
A writing operation for storage area L
1
is described first. Referring to
FIG. 24
, data is written into storage area L
1
by maintaining the potential on bit line BL
0
at a write potential VCCW and maintaining the potential on bit line BL
1
at a ground potential GND to cause a write current Ifw to flow from bit line BL
0
to bit line BL
1
through nonvolatile memory cell MC. Data is thus written into storage area L
1
.
Next, a reading operation for storage area L
1
is described. Referring to
FIG. 25
, data in storage area L
1
is read by maintaining the potential on bit line BL
0
at ground potential GND and maintaining the potential on bit line BL
1
at a read potential VCCR to cause a read current Ifr to flow from bit line BL
1
to bit line BL
0
. The data is accordingly read from storage area L
1
.
It is seen from the above that, in storage area L
1
, the direction in which the current flows in the writing operation is opposite to that of the current flowing in the reading operation.
A writing operation for storage area L
2
is now described. Referring to
FIG. 26
, data is written into storage area L
2
by maintaining the potential on bit line BL
0
at ground potential GND and maintaining the potential on bit line BL
1
at write potential VCCW to cause a write current Irw to flow from bit line BL
1
to bit line BL
0
. Then, data is written into storage area L
2
.
A reading operation for storage area L
2
is described below. Referring to
FIG. 27
, data is read from storage area L
2
by maintaining the potential on bit line BL
0
at read potential VCCR and maintaining the potential on bit line BL
1
at ground potential GND to cause a read current Irr to flow from bit line BL
0
to bit line BL
1
. Then, data is read from storage area L
2
.
It is also seen from the above that, in storage area L
2
, the direction in which the current flows in the writing operation is opposite to that of the current flowing in the reading operation. Moreover, respective writing currents in writing data into storage areas L
1
and L
2
flow in opposite directions respectively. Similarly, respective reading currents in reading data from storage areas L
1
and L
2
flow in opposite directions respectively.
It is accordingly essential to control the potential on each bit line BL for the writing operation of the NROM.
FIG. 28
illustrates a writing operation for nonvolatile memory cells arranged in the memory cell array as shown in FIG.
22
.
Referring to
FIG. 28
, an operation of writing data of an H (logical high) level into storage area L
1
of a nonvolatile memory cell MC
1
shown in
FIG. 28
is described below.
A word line WL
1
is selected, and the potential on bit line BL
1
is maintained at write potential VCCW while the potential on bit line BL
2
is maintained at ground potential GND. At this time, in nonvolatile memory cell MC
1
, write current Ifw flows from the node connected to bit line BL
1
to the node connected to bit line BL
2
. Data is accordingly written into storage area L
1
. Here, in a nonvolatile memory cell MC
0
adjacent to nonvolatile memory cell MC
1
, an unwanted current I
1
flows if the potential on bit line BL
0
is lower than the potential on bit line BL
1
. The unwanted current I
1
impedes power savings and, in addition, the unwanted current I
1
could cause any malfunction of the memory cell array. Control is thus important of the potential on each bit line BL for the writing operation of the NROM.
Moreover, conventional semiconductor memory devices such as the NROM for example can write only one bit at a time into a memory cell, which means that there is a problem of a low throughput.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a semiconductor memory device capable of writing data without malfunction. Another object of the present invention is to provide a semiconductor memory device with an improved throughput.
According to one aspect of the present invention, a semiconductor memory device includes a plurality of word lines arranged in the direction of rows, a plurality of bit lines arranged in the direction of columns, a plurality of memory cells, and a write circuit. The memory cells are arranged in the row direction and in the column direction and each have at least one storage area for storing data therein. The write circuit writes mu

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