Static information storage and retrieval – Addressing
Reexamination Certificate
2006-10-05
2008-11-11
Luu, Pho M. (Department: 2824)
Static information storage and retrieval
Addressing
C365S230020, C365S230040, C365S230080
Reexamination Certificate
active
07450461
ABSTRACT:
In a system of using a plurality of memories with a plurality of CPUs, a plurality of memory arrays are placed on the same memory chip with each memory array being individually provided with a data-related circuit, an address-related circuit and a control-related circuit. These memory arrays however share a data terminal, an address terminal and a control terminal for chip external connection. A data, address and control signals are distributed to the memory arrays via three MUX of signal selection circuits controlled with an array selection signal (clock). A signal is supplied to one memory array at rising timing of the clock while a signal is supplied to another memory array at falling timing of the clock. Thus, in memory integration of placing a plurality of memory arrays on one chip, independent operation for each memory array is attained, and no bus arbitration between CPUs is necessary.
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patent: 2001/0036109 (2001-11-01), Jha et al.
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Kotani Hisakazu
Nishikawa Kazuyo
Nishimura Motonobu
Ueminami Masahiro
Luu Pho M.
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
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