Semiconductor memory device and test method thereof

Details Semiconductor memory device and test method thereof Semiconductor memory device and test method thereof

2008-09-18

2010-12-28

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189090, C365S201000

Reexamination Certificate

active

07859938

ABSTRACT:
When a predetermined code is set to a mode register, a switching signal generating circuit is activated, and a switching signal TCLKE becomes at a high level. When the switching signal TCLKE becomes at a high level, input data supplied from a data input and output terminal DQ is used as an internal clock ICLK. Accordingly, during a test in a wafer state, a clock signal can be received from the data input and output terminal DQ, even when a clock terminal, an address terminal, and a command terminal are connected in common to plural semiconductor memory devices. Therefore, a code for artificially performing a fine adjustment of a reference voltage can be individually supplied for each chip.

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