Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-03-26
2002-06-04
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110, C365S200000
Reexamination Certificate
active
06400602
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, such as a non-volatile semiconductor memory device, e.g., a flash memory, an FRAM (a type of a ferroelectric memory device) and an MRAM (a type of a magnetic memory device), or a volatile semiconductor memory device which includes a non-volatile memory region; and a method for restoring such a semiconductor memory device having any defective memory cells.
2. Description of the Related Art
Unlike volatile memories such as DRAMs (dynamic random access memories) and SRAMs (static random access memories), whose data will be reset when the power supply to the memory devices is stopped, non-volatile semiconductor memory devices (which may simply be referred to as “non-volatile memories”) can retain data in memory cells thereof even after the power supply thereto is stopped. Examples of non-volatile memories include flash memories (which are in wide use, e.g., in cellular phones), FRAMs (which are used in IC cards, etc.), and MRAMs which are under vigorous development. The description in the present specification will chiefly deal with flash memories as exemplary non-volatile memories.
In general, semiconductor memory devices are produced through a minute fine semiconductor process. Therefore, there may always be a certain percentage of defective memory cells included in semiconductor memory devices. Therefore, it has been conventional practice to provide a number of extra or reserve memory cells in the semiconductor memory device, in addition to the regular memory cells, and replace defective memory cells with such reserve memory cells. Thus, the semiconductor memory device including defective memory cells, which would otherwise have been discarded, can be “restored”.
However, in order to avoid increase in the chip size, there can only be so many reserve memory cells provided in a semiconductor memory device. Hence, under circumstances where only a small resource can be allocated for the reserve memory cells, any chips which cannot be restored even by using reserve memory cells must be discarded as defective chips.
Several methods have been proposed to enable restoration of those chips which cannot be restored by the use of reserve memory cells. According to such methods, those chips which would otherwise be discarded as defective chips are relabeled as smaller-capacity semiconductor memory devices, in which any defective memory cell regions are prevented from being accessed.
For example, in the field of volatile memories, Japanese Laid-Open Patent Publication No. 11-162193 proposes a method which involves selecting only normal memory cell blocks by cutting a fuse with a laser means or the like. In the field of non-volatile memories, Japanese Laid-Open Patent Publication No. 9-7390 proposes a method which involves storing any cell information to be relocated in a non-volatile memory cell which is separately prepared in addition to regular memory cells, and selecting only the normal memory cell blocks.
However, the aforementioned conventional methods for restoring a semiconductor memory device including defective memory cells amount to, at best, simply “unselecting” a given address so as to convert what was originally an x Mbit capacity to a much reduced capacity of x/2 Mbits or x/2
n
Mbits (where n=a positive integer). Therefore, even if one defective memory cell is contained in the entire semiconductor memory device, the overall capacity of the semiconductor memory device is reduced to ½, ¼, ⅛, etc., thereby wasting a large number of normally-functioning memory cells.
Moreover, the aforementioned conventional methods cannot be employed to restore semiconductor memory devices having a multi-block configuration, in which a plurality of blocks having different capacities are provided within the semiconductor memory device, or a bank configuration (which has gradually been becoming a mainstream in flash memories in recent years), which allows a read operation to be performed during a program or erase operation.
Furthermore, with any of the aforementioned conventional methods, a semiconductor memory device including a defective memory cell cannot be restored in such a manner as to allow defective memory cell regions to accept only limited types of operations which are determined in accordance with the defect mode.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, there is provided a semiconductor memory device including: a plurality of memory cell regions, each including at least one memory cell; a non-volatile memory section which accepts external writing; and unselecting means for designating at least one of the plurality of memory cell regions to be inaccessible based on data written to the non-volatile memory section, wherein at least one operation type is performed for at least one accessible memory cell region, which is not designated to be inaccessible, among the plurality of memory cell regions.
In one embodiment of the invention, the semiconductor memory device further includes address conversion means for assigning a consecutive sequence of external addresses to the at least one accessible memory cell region.
In another embodiment of the invention, if an internal address which is generated by adding a predetermined value to an external address coincides with an existing internal address when assigning the consecutive sequence of external addresses to the at least one accessible memory cell region, one of the plurality of memory cell regions corresponding to the generated internal address is designated to be inaccessible.
In still another embodiment of the invention, based on the data written to the non-volatile memory section, the unselecting means designates at least one of the plurality of memory cell regions to be inaccessible to one operation type among the at least one operation type, and yet accessible to the other operation types among the at least one operation type.
In still another embodiment of the invention, the semiconductor memory device includes a plurality of memory cell blocks capable of accepting a block erase operation, and when designating at least one of the plurality of memory cell regions to be inaccessible based on the data written to the non-volatile memory section, the unselecting means designates at least one of the plurality of memory cell blocks to be inaccessible.
In still another embodiment of the invention, the plurality of memory cell blocks includes at least one memory cell block having a different capacity.
In still another embodiment of the invention, the semiconductor memory device includes a plurality of banks, each including the plurality of memory cell blocks, such that the plurality of memory cell blocks are capable of dual work operation, and, when designating at least one of the plurality of memory cell regions to be inaccessible based on the data written to the non-volatile memory section, the unselecting means designates at least one of the plurality of banks to be inaccessible.
In still another embodiment of the invention, at least one of the plurality of banks includes at least one memory cell block having a different capacity.
In still another embodiment of the invention, the address conversion means is capable of changing an address position of the at least one memory cell block having the different capacity.
In still another embodiment of the invention, the non-volatile memory section is provided in a portion of a non-volatile memory cell which is capable of programming at once.
According to another aspect of the present invention, there is provided a method for restoring the aforementioned semiconductor memory device when the semiconductor memory device includes a defective memory cell, including the steps of: storing an address of the defective memory cell in the non-volatile memory section; and designating, by means of the unselecting means, one of the plurality of memory cell regions that includes the defective memory cell to be inaccessible, based on th
Maeda Kengo
Mori Yasumichi
Takata Hidekazu
Le Thong
Morrison & Foerster / LLP
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