Semiconductor memory device and reading and writing method...

Details Semiconductor memory device and reading and writing method... Semiconductor memory device and reading and writing method...

2001-10-25

2002-07-16

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S189040, C365S189050, C365S230080

Reexamination Certificate

active

06421274

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device of large capacity such as a semiconductor disk device employing a flash memory in which reading, writing and erasing are performed in block units, and employing a memory of a large capacity as a nonvolatile semiconductor memory for realizing high performance with reduction in manufacturing costs.
2. Description of the Prior Art
Examples of conventionally used nonvolatile semiconductor memories are, for instance, M5M29F25611VP manufactured by Mitsubishi Electric Corporation and HN29W25611 manufactured by Hitachi Ltd., which are flash memories performing read and write processes in block units of 2 k bytes. In a semiconductor memory device mounted with such a flash memory, the flash memory includes a plurality of blocks each of which are of 2 k bytes as illustrated in
FIG. 7
for enabling parallel processing of data transmission to/from the host terminal and data transmission to/from the flash memory, wherein each of two buffer RAMs (R
1
, R
2
) has a capacity size corresponding to a single block.
In a conventional semiconductor memory device as illustrated in
FIG. 7
, the capacity of each buffer RAM corresponds to a capacity size of a single block, that is, an integer multiple of a single sector size (e.g. corresponding to four sector sizes in the figure).
Transmission of data between the host terminal and the buffer RAM and transmission of data between the flash memory and the buffer RAM are performed in a manner that separate buffer RAMs are respectively selected between the two buffer RAMs (R
1
, R
2
), wherein when data is sent and received between either one buffer RAM (e.g. R
1
) and the host terminal, data is sent and received between the other buffer RAM (e.g. R
2
) and the flash memory.
Transmission of data between the buffer RAM and the host terminal and between the buffer RAM and the flash memory is performed in a manner that data of a plurality of sectors corresponding to a single block is transmitted in one lump sum, and commands for the flash memory are issued in blocks (i.e. in a unit of four sectors).
FIG. 7A
is a schematic view illustrating a conventional operation of reading data from the flash memory to the host terminal, and
FIG. 7B
is a schematic view illustrating a conventional operation of writing data from the host terminal to the flash memory, wherein the flash memory is comprised of a plurality of blocks each of which has a block size of 2 k bytes (i.e., four sector sizes).
In the operation for reading data from the flash memory as illustrated in
FIG. 7A
, transmission of data as indicated by a broken-line arrow indicates that data of a single block is preliminarily read from the flash memory and stored in one buffer RAM, i.e., buffer RAM (R
1
), and then both transmissions of data as indicated by solid-line arrows are simultaneously performed. In other words, simultaneously with reading out the data which are preliminarily stored in the buffer RAM (R
1
) from the buffer RAM (R
1
) and transmitting the same to the host, data of next block are read out from the flash memory and transmitted to the other buffer RAM (R
2
) to be stored therein.
Similarly, in performing an operation of writing data to the flash memory from the host terminal as illustrated in
FIG. 7B
, transmission of data as indicated by a broken-line arrow indicates that data of a single block are preliminarily stored in one buffer RAM (R
1
) from the host, and then both transmissions of data as indicated by the solid-line arrows are simultaneously performed. In other words, simultaneously with reading out data which are preliminarily stored in the buffer RAM (R
1
) and transmitting the same to the flash memory, data of next block are transmitted from the host terminal and transferred to the other buffer RAM (R
2
) to be stored therein.
Japanese Patent Unexamined Laid-open Publication No. 64-74649 (1989) discloses a technique related to a magnetic disk device comprising two buffer memories respectively of a capacity corresponding to a plurality of sectors, wherein data of a single sector is read out and stored in one buffer memory, and data of another sector is read and stored in the other buffer memory during transmission of the data. In this publication, however, the reason for providing two buffer memories each having a capacity corresponding to a plurality of sectors, is to simplify analysis of breakdowns by keeping hysteresis of transmitted data.
In the general conventional arrangements, since each of buffer RAMs has a capacity of a plurality of sectors, the capacity of the buffer memories becomes large. Therefore, it would be necessary to provide buffer RAMs of large structure when the capacities of flash memories further increase in future to have large block sizes of 4 k bytes or 8 k bytes and so on. Thus, increases in costs of the entire device including controllers and other members are unavoidable.
In case read commands or write commands are executed in each buffer size while these buffer sizes remained small, an overhead is excessively added for executing the command, resulting in a drawback that the efficiency is lowered and further that writing and reading speeds with respect to the host terminal side are delayed.
The present invention has been made for the purpose of solving the problems, and it is an object thereof to provide a semiconductor memory device in which the size of each of the buffer RAMs is decreased to correspond to a single sector size, which can be manufactured at low costs, which is capable of performing rapid transmission and rapid processing of writing and reading data, and further to provide a method for reading and writing thereof.
It is another object of the present invention to provide a semiconductor memory device capable of exhibiting the above performances with which it is possible to improve reliability of data by performing error correction.
SUMMARY OF THE INVENTION
In order to achieve the above-mentioned objectives, the present invention provides a semiconductor memory device which is connected to a host terminal through a system bus for data transmission. The semiconductor memory device comprises: a nonvolatile semiconductor memory having a structure of a plurality of blocks, wherein read and write commands are executed in block units, with a capacity size of a single block being an integer multiple of a single sector size corresponding to a processing unit of the host terminal for reading and writing data; a first buffer memory and a second buffer memory for mediation of data transmission between the host terminal and the nonvolatile semiconductor memory, each of the first and second buffer memories having a capacity corresponding to a single sector size of the nonvolatile semiconductor memory, and a controller for controlling data transmission in sector units between the host terminal and the buffer memories and between the nonvolatile memory and the buffer memories by alternately selecting the first and second buffer memories, and when one of the buffer memories performs transmission of data corresponding to one sector with the host terminal, the other buffer memory simultaneously performs transmission of data corresponding to another sector with the nonvolatile semiconductor memory.
The controller generates control signals to apply a read and write command with respect to a block of the nonvolatile semiconductor memory in response to a request for reading and writing data from the host terminal, and wherein transmission of data between the host terminal and the nonvolatile semiconductor memory is sequentially performed via the buffer memories every sector data.
The controller is adapted to maintain control levels of the control signals for the nonvolatile semiconductor memory in a manner that, after transmission of a single sector data, transmission of another sector data is continued to thereby perform simultaneous and parallel data transmission.
With this arrangement

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