Semiconductor memory device and operating method thereof

Details Semiconductor memory device and operating method thereof Semiconductor memory device and operating method thereof

1992-10-15

1995-07-04

Popek, Joseph A.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

365 63, 365214, 36523001, 36523004, 365239, G11C 800

Patent

active

054306868

ABSTRACT:
In a DRAM, buffer circuits constituting a column address buffer are provided near address input pads receiving external address signals to be input thereto, and switch circuits arranged near the address input pads are connected between the address input pads and a row address buffer. Driving capability of each buffer circuits is set larger than in the prior art. Each switch circuit is controlled to be OFF while a column address signal is being supplied to a corresponding one of the address input pads. While the column address signal is externally applied to the address input pads, the capacitance and resistance of the interconnection layer which affects the waveform of the internal column address signal can be reduced, and hence time required for selecting one column of memory cells in each of memory cell array blocks in response to the external column address signal can be reduced, thus reducing the access time in the DRAM.

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