Semiconductor memory device and operating method therefor

Details Semiconductor memory device and operating method therefor Semiconductor memory device and operating method therefor

1992-11-18

1994-12-06

Sikes, William L.

Static information storage and retrieval

Addressing

Sync/clocking

365 51, 365 63, 36518905, G11C 800, G11C 502

Patent

active

053717163

ABSTRACT:
Two sets of data buses, two equalizing circuits and two amplifying circuits are provided. A selection signal generating circuit generates selection signals for alternately selecting data buses. When the data bus is selected, the equalizing circuit is activated and the amplifying circuit is activated. The data bus is selected, the equalizing circuit is activated and the amplifying circuit is activated.

REFERENCES:
patent: 4715017 (1987-12-01), Iwahashi
patent: 4893277 (1990-01-01), Kajigaya
patent: 4922461 (1990-05-01), Hayakawa
patent: 4954987 (1990-09-01), Auvinen
patent: 5043947 (1991-08-01), Oshima
patent: 5068831 (1991-11-01), Hoshi

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