Semiconductor memory device and operating method

Details Semiconductor memory device and operating method Semiconductor memory device and operating method

1993-03-29

1994-08-23

LaRoche, Eugene R.

Static information storage and retrieval

Powering

36518909, G11C 700

Patent

active

053413407

ABSTRACT:
A substrate bias generating circuit includes V.sub.BB generating circuits and a switching circuit. The switching circuit, in the standby period, applies an internal power supply voltage applied by an internal voltage down converting circuit to the V.sub.BB generating circuits. The switching circuit, in the active period, applies an external power supply voltage to the V.sub.BB generating circuits.

REFERENCES:
patent: 4455628 (1984-06-01), Ozaki et al.
patent: 4585954 (1986-04-01), Hashimoto et al.
patent: 4817055 (1989-03-01), Arakawa et al.
patent: 5146110 (1992-09-01), Kim et al.

Affiliated with

Also associated with

Rating

Semiconductor memory device and operating method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device and operating method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device and operating method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-507800