Semiconductor memory device and method of using the same

Details Semiconductor memory device and method of using the same Semiconductor memory device and method of using the same

1995-04-03

1996-11-05

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular connection

36518518, 36518527, G11C 1134

Patent

active

055724647

ABSTRACT:
In a semiconductor memory device and a method for using the semiconductor memory device, the semiconductor memory device includes a plurality of memory cells series-connected to each other, and each formed by a P-channel transistor in which a control gate electrode is stacked via an insulating film on a floating gate electrode. One end of the plural memory cells series-connected to each other is connected to one of a source and a drain of a first selecting transistor. The other of the source and the drain of the first selecting transistor are connected to a bit line. The other end of the plural memory cells series-connected to each other is connected to one of a source and a drain of a second selecting transistor. The other of the source and the drain of the second selecting transistor is connected to a power source line.

REFERENCES:
patent: 4959812 (1990-09-01), Momodomi et al.
New Device Technologies For 5V-Only 4 Mb EEPROM With NAND Structure Cell, Momodomi et al., IEEE 1988, IEDM pp. 412-415.
A High-Density NAND EEPROM With Block-Page Programming For Microcomputer Applications, Iwata et al., IEEE, Journal of Solid-State Circuits, vol. 25, No. 2, Apr. 1990 pp. 417-424.
A 2.3 um.sup.2 Memory Cell Structure for 16 Mb NAND EEPROMS, Shirota et al., IEEE 1990, IEDM pp. 103-106.

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