Semiconductor memory device and method of testing the same

Details Semiconductor memory device and method of testing the same Semiconductor memory device and method of testing the same

1992-07-15

1994-12-13

Canney, Vincent P.

Excavating

365201, 371 211, G01R 3128

Patent

active

053735099

ABSTRACT:
Provided are a row address circuit for driving all word lines at one time so as to select all memory cells in a memory circuit when receiving a writing control signal for test and a column address circuit for writing some particular pattern of test data which corresponds to a data specifying signal into the memory cells at one time via all pairs of bit lines when receiving the writing control signal. Also, provided in the memory circuit is a test circuit for judging at one time whether the data held in each memory cell conforms with an expected value thereof. Thus a time required for testing a semiconductor memory device of a large capacity is reduced.

REFERENCES:
patent: 5072137 (1991-12-01), Slemmer
patent: 5185722 (1993-02-01), Ota et al.
patent: 5258954 (1993-11-01), Furuyama
patent: 5265100 (1993-11-01), McClure et al.
S. Mori et al., A 45ns 64Mb DRAM With A Merged Match-Line Test Architecture, IEEE ISSCC Digest of Technical Papers, pp. 110-111 (Feb. 1991).

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