Semiconductor memory device and method of performing data...

Static information storage and retrieval – Format or disposition of elements

Reexamination Certificate

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C365S063000, C365S189030

Reexamination Certificate

active

07907433

ABSTRACT:
A semiconductor device includes a plurality of package terminals included in a package, a plurality of chips provided on the package, each of the chips including a memory cell array and a plurality of data input/output terminals, and a plurality of data line control switch disposed between the plurality of package terminals and the plurality of data input/output terminals. The plurality of data line control switches of each of the chips connects the data input/output terminals of each of the chips to corresponding ones of the plurality of package terminals in a normal mode. The plurality of data line control switches connects different groups of the data input/output terminals in different ones of the chips to respective groups of the package terminals in a test mode. The respective groups of the data input/output terminals belong to the plurality of data input/output terminals. The respective groups of the package terminals are different between different ones of the chips.

REFERENCES:
patent: 5511029 (1996-04-01), Sawada et al.
patent: 6529438 (2003-03-01), Suzuki et al.
patent: 2003/0099143 (2003-05-01), Fujioka et al.
patent: 2006/0262587 (2006-11-01), Matsui et al.
patent: 6-333400 (1994-12-01), None
patent: 2000-040397 (2000-02-01), None
patent: 2003-168299 (2003-06-01), None

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