Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Isolation by pn junction only
Reexamination Certificate
2009-01-16
2011-10-25
Smith, Zandra (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Isolation by pn junction only
C438S218000
Reexamination Certificate
active
08043930
ABSTRACT:
A semiconductor memory device includes first and second element isolation insulating films, first and second gate insulating films, first and second gate wiring and first and second mask layer. First and second upper surfaces of the first and second element isolation insulating films are higher than an upper surface of the substrate, first and second bottom surfaces of the first and second element isolation insulating films are lower than the upper surface of the substrate, a second height from the upper surface of the substrate to the second upper surface is larger than a first height from the upper surface of the substrate to the first upper surface. A height from the upper surface of the substrate to an upper surface of the first mask layer equals a height from the upper surface of the substrate to an upper surface of the second mask layer.
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Office Action issued Nov. 30, 2010, in Japan Patent Application No. 2005-322100 (with English translation).
Kabushiki Kaisha Toshiba
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
Perkins Pamela E
Smith Zandra
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