Semiconductor memory device and method of manufacturing the...

Details Semiconductor memory device and method of manufacturing the... Semiconductor memory device and method of manufacturing the...

2007-10-18

2009-10-27

Le, Thao X (Department: 2892)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

C257S316000, C257SE21704, C438S294000, C438S587000

Reexamination Certificate

active

07608488

ABSTRACT:
A manufacturing method of a semiconductor memory device for manufacturing a first semiconductor device and a second semiconductor device wherein a cell array ratio is smaller than that of the first semiconductor device, said manufacturing method has forming the height of first element-isolating insulating films of first memory cell array region of said first semiconductor device so as to be a predetermined height, by performing etching treatment under predetermined conditions using a first etching mask having a first opening for exposing the entirety of said first memory cell array region, and forming the height of second element-isolating insulating films of second memory cell array region and part of peripheral circuit region of said second semiconductor device so as to be the predetermined height, by performing etching treatment under said predetermined conditions using a second etching mask having a second opening for exposing the entirety of said second memory cell array region and a third opening for exposing part of said peripheral circuit region.

REFERENCES:
patent: 7138314 (2006-11-01), Song et al.
patent: 2005/0093047 (2005-05-01), Goda et al.
patent: 2005/0106822 (2005-05-01), Lee et al.

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