Semiconductor memory device and method of fabricating the same

Semiconductor device manufacturing: process – Having magnetic or ferroelectric component

Reexamination Certificate

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C438S238000, C438S239000

Reexamination Certificate

active

07022531

ABSTRACT:
A semiconductor memory device including a memory cell block having a plurality of memory transistors formed on a semiconductor substrate. The memory transistors include first and second impurity-diffused regions and a gate formed therebetween. A plurality of memory cells are also included in the memory cell block and have lower electrodes connected to the first impurity-diffused regions, ferroelectric films formed on the lower electrodes and first upper electrodes formed on the ferroelectric films and connected to the second impurity-diffused regions. Further included are block selecting transistors formed on the semiconductor substrate and being connected to one end of the memory cell block. Second upper electrodes are also formed adjoined to the block selecting transistors and being disconnected from the first upper electrode of the memory cells.

REFERENCES:
patent: 5281555 (1994-01-01), Cho
patent: 5361234 (1994-11-01), Iwasa
patent: 5410161 (1995-04-01), Narita
patent: 5689126 (1997-11-01), Takaishi
patent: 5789775 (1998-08-01), Evans, Jr. et al.
patent: 5903492 (1999-05-01), Takashima
patent: 6198652 (2001-03-01), Kawakubo et al.
patent: 6235573 (2001-05-01), Lee et al.
patent: 6366488 (2002-04-01), Zambrano et al.
patent: 6500677 (2002-12-01), Bergmann et al.
patent: 6664158 (2003-12-01), Dehm et al.
patent: 6677630 (2004-01-01), Kanaya et al.
patent: 6724026 (2004-04-01), Jacob et al.
patent: 6759251 (2004-07-01), Ozaki
patent: 4-05-129552 (1993-05-01), None
patent: 4-08-181290 (1996-07-01), None
patent: 4-11-354727 (1999-12-01), None
patent: 1999-0030957 (1999-05-01), None
Takashima et al., A Sub-40ns Random-Access Chain FRAM Architecture with a 7ns Cell-Plate-Line Drive, 1999, IEEE, International Solid State Circuits Conference, pp. 102, 103, 150.
Takeshima et al., Gain Cell Block Architecture for Gigabit-Scale Chain Ferroelectric RAM, Jun. 1999, Symposium on VLSI Circuits Digest of Technical Papers, pp. 103-104.

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