Semiconductor memory device and method of controlling write...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185220, C365S185170

Reexamination Certificate

active

07145806

ABSTRACT:
A semiconductor memory device includes: a memory cell array having a plurality of word lines and a plurality of bit lines, which cross each other, and electrically rewritable and non-volatile memory cells disposed at crossings thereof; a read/write circuit configured to write data into a selected memory cell with applying a write voltage to a selected word line, and detect a discharge state of a selected bit line to read data of the selected memory cell after having precharged the selected bit line to a certain voltage; and a controller configured to control the read/write circuit to execute a write sequence by repeat of a write operation and a verify-read operation for the selected memory cell in such a way as to start a precharge operation of the selected bit line for the verify-read operation prior to the ending time of the write operation in the write sequence.

REFERENCES:
patent: 6128229 (2000-10-01), Nobukata
patent: 2002-133888 (2002-05-01), None

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