Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2003-05-22
2004-10-26
Mai, Son (Department: 2818)
Static information storage and retrieval
Format or disposition of elements
C365S230030
Reexamination Certificate
active
06809946
ABSTRACT:
This application claims priority to prior application JP 2002-149310, the disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a control method for the same and, more particularly, to a dynamic RAM (hereinafter, will be referred to as the “DRAM”) capable of reading/writing at high speed and a control method for the same.
Conventionally, this type of semiconductor memory device has a layered I/O structure. In a memory LSI using such a layered I/O structure, local I/O lines connected to sense amplifiers are connected to main amplifiers via main I/O lines. Furthermore, main amplifiers are connected to output circuits via global I/O lines, and these output circuits are connected to I/O terminals. Thus, as a semiconductor device having a layered I/O structure, a semiconductor memory device having sub amplifier circuits provided between the sense amplifier and the main amplifier in order to amplify micro-signals of the sense amplifier has been proposed (refer to, for example, Japanese Unexamined Patent Publication No. 11-214652 (hereinafter referred to as citation 1)). Citation 1 proposes the provision of a sub amplifier block in an area wherein a sense amplifier region and a sub word driver region intersect with each other, and discloses that the sub amplifier circuits are selectively activated.
As a semiconductor memory device having the configuration described above, a 512M DDR (Double Data Rate) memory device has been proposed. In this memory device, for example, four banks are disposed on a chip, and each bank is further divided into a plurality of memory mats. In this case, each bank has a 128M-bit memory capacity and is divided into memory mats, each having a 256K-bit memory capacity.
In the case of the proposed semiconductor memory device, a column decoder is disposed at the center of each bank, and the column decoder activates a column selector line to thereby read data from a sense amplifier to an I/O line.
Meanwhile, in this type of a large-capacity semiconductor memory device, the eight column selector lines of each bank are simultaneously activated. In this event, a selection may be made between a mode for reading the data from each bank into eight I/O terminals DQ
0
through DQ
7
(hereinafter referred to as the “x8 mode”) and a mode for outputting the data from each bank to four of the I/O terminals DQ
0
through DQ
7
(hereinafter referred to as “x4 mode”).
According to citation 1 described above, regardless of whether the x8 mode or the x4 mode is selected, the sense amplifiers corresponding to the eight column selector lines are selected, and the sub amplifier circuits in the crossing areas associated with the sense amplifiers are activated. The outputs of the activated sub amplifier circuits are supplied to a main amplifier through a main I/O line, and 8-bit data or 4-bit data is selected in the main amplifier or the output circuit.
With such a structure, the unnecessary data in the x4 mode is undesirably output up to the main amplifier or the output circuit through the main I/O line, resulting in more current drain in the x4 mode. Furthermore, citation 1 does not refer at all to shifting the control of the sub amplifier circuit between the x8 mode and the x4 mode, and provides no considerations to disposing the sub amplifier circuits in a concentrated manner.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor memory device which permits a reduction in the current drain in the x4 mode, as compared with a conventional semiconductor memory device.
It is another object of the present invention to provide a semiconductor memory device which permits a reduction in a layout area by improving the layout in a sub amplifier circuit.
It is a further object of the present invention to provide a control method for a semiconductor memory device that permits a reduction in the current drain when the sub amplifier circuits are simultaneously activated.
According to one aspect of the present invention, there is provided a semiconductor memory device having a bank that can be divided into a memory array including a plurality of memory mats, including a sense amplifier set connected to each memory array, sub amplifier circuit units connected to the sense amplifier set, and a main amplifier circuit unit connected to the sub amplifier circuits, wherein the sub amplifier circuit is disposed in a concentrated fashion in a central region wherein the bank is divided into first and second partial regions, the sub amplifier circuit comprises first and second groups of sub amplifiers respectively connected to a plurality of sense amplifier sets in the first and second partial regions, and a sub amplifier control circuit for controlling the first and second groups of sub amplifiers, and the sub amplifier control circuit is configured to commonly control the first and second groups of sub amplifiers.
Preferably, the semiconductor memory device in accordance with the present invention is further provided with a plurality of column selector lines extending in parallel to the central region on the memory mats, wherein these plural column selector lines, when simultaneously activated, connect a plurality of memory arrays in the first and second partial regions with the sub amplifiers of the first and second groups through the intermediary of the sense amplifier sets so that the sub amplifiers of the first and second groups are commonly controlled by the sub amplifier control circuit.
Preferably, the sub amplifier control circuit carries out control for selectively enabling or disabling the sub amplifiers of the first and second groups connected to the sense amplifier sets.
Preferably, the semiconductor memory device according to the present invention further includes a starter signal generator circuit that supplies a signal at a predetermined bit position of a column selection address signal to the sense amplifier control circuit as a starter signal for starting up the sub amplifier control circuit.
Preferably, when the column selector lines are simultaneously activated, two sense amplifier sets each are activated in the first and second partial regions, respectively, thereby connecting four sub amplifiers of the first group to the activated two sense amplifier sets with respect to the first partial region. Similarly, four sub amplifiers of the second group are connected to the two activated sense amplifier sets with respect to the second partial region, and the sub amplifier control circuit controls a total of eight sub amplifiers of the first and second groups to connect the sense amplifier sets in the first and second partial regions to a main amplifier through the intermediary of the eight sub amplifiers.
Preferably, the sub amplifier control circuit discriminates between write/read of data to/from the memory mats, and carries out control to bypass an amplifying section of each sub amplifier in a write mode, while it carries out control to enable the amplifying section of each sub amplifier in a read mode.
According to another aspect of the present invention, there is provided a semiconductor memory device having a bank that can be divided into memory arrays including a plurality of memory mats. The semiconductor memory device is provided with sense amplifier sets disposed on both sides of the memory arrays, sandwiching the memory arrays, first and second sub amplifier circuit units connected to the sense amplifier sets disposed on both sides of the memory arrays, and a main amplifier circuit unit connected to the first and second sub amplifier circuit units through via main input/output lines (MIO), wherein the first and second sub amplifier circuit units are disposed in a concentrated fashion in a central region in which the bank is divided into first and second partial regions, the first and second sub amplifier circuit units comprise a plurality of sub amplifiers disposed in the plurality of sense amplifier sets respectively disposed on bo
Fujisawa Hiroki
Yokou Hideyuki
Choate Hall & Stewart
Elpida Memory Inc.
Mai Son
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