Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
1998-04-07
2001-02-06
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S225700
Reexamination Certificate
active
06185146
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device for accessing a memory cell in a memory array belonging to one of a plurality of banks into which a plurality of memory arrays are classified, and a method for producing such a semiconductor memory device.
2. Description of the Related Art
A conventional semiconductor device is disclosed in, for example, Japanese Laid-Open Publication No. 6-76567. In the semiconductor memory device disclosed in the above-mentioned publication, memory arrays are classified into two or four banks in accordance with whether the data input and output is performed at a unit of 8 bits (×8 structure) or 4 bits (×4 structure).
The number of banks is determined in accordance with the number of a series of pieces of data wrap length accessible by one address input in lieu of being set in accordance with the number of bits included in one piece of data.
In a structure where the memory arrays are classified into a plurality of banks, data transfer rate is improved by performing an interleave operation, in which banks are accessed alternately.
FIG. 6
is a block diagram of a device for switching the number of banks, which is also disclosed in Japanese Laid-Open Publication No. 6-76567.
In
FIG. 6
, a pad PD is connected to a power supply potential Vcc or a ground potential Vss by wire bonding. A pad potential detection circuit
100
detects a potential of the pad PD and outputs a “high” signal (high level) or “low” signal (low level). In response to the potential of the signal sent from the pad potential detection circuit
100
, a bank selection circuit
102
performs a 2-bit or 1-bit decoding operation, thereby generating a bank selection signal.
The bank selection circuit
102
receives two-bit selection address signals A
11
and A
10
. When the output signal from the pad potential detection circuit
100
represents a ×4 structure, the bank selection circuit
102
decodes the two-bit signals A
11
and A
10
, and one of four-bit bank selection signals BA
0
through BA
3
is set to a selecting state. In other words, the bank selection circuit
102
generates the four-bit bank selection signals BA
0
through BA
3
in order to set four banks. By the bank selection signals, the banks are sequentially selected and thus activated.
When the output signal from the pad potential detection circuit
100
represents a ×8 structure, the bank selection circuit
102
invalidates one of the two-bit address signals A
10
and generates two-bit bank selection signals B
0
and B
1
in accordance with the other signal A
11
. In other words, the bank selection circuit
102
generates the two-bit bank selection signals B
0
and B
1
in order to set two banks. By the bank selection signals, the banks are sequentially selected and thus activated.
The system shown in
FIG. 6
is applicable to a structure in which the number of banks is determined in accordance with the wrap length. In such a structure, the pad PD is connected to the power supply potential Vcc or the ground potential Vss depending on whether the wrap length is 8 or 4. The pad potential detection circuit
100
is used as a wrap length setting circuit, and the bank selection circuit
102
generates a bank selection signal.
However, in the above-described structure, the potential of the pad PD is determined by wire bonding, which determines the number of the banks. Accordingly, as the number of banks to be set increases, the number of required pads also increases. For example, when the number of banks is set to be 2, only one pad is required. When the number of banks is set to be four, two pads are required.
In this manner, the number of required pads increases along with the number of banks to be set, which results in an increase in the chip area required for the pads.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a semiconductor memory device includes a plurality of memory arrays including a plurality of memory cells; a plurality of fuses having one of a disconnected state and a connected state for classifying the plurality of memory arrays into a plurality of banks; and a selection circuit for selecting one of the plurality of banks based on the state of the plurality of the fuses and an address signal.
According to another aspect of the invention, a method for producing a semiconductor memory device includes the steps of forming a plurality of memory arrays including a plurality of memory cells; and forming a fuse having one of a disconnected state and a connected state for classifying the plurality of memory arrays into a plurality of banks, the fuse being formed by masking.
According to the present invention, a plurality of memory arrays are classified into a prescribed number of (two or more) banks by selectively disconnecting fuses. When address signals are partially or totally input to the semiconductor memory device according to the present invention in the state where the fuses are selectively disconnected, one of the banks is selected based on an input signal. The state where the fuses are selectively disconnected includes the state where no fuse is disconnected.
The fuses are formed together with other circuits of the semiconductor memory device. Since a fuse is smaller than a pad, the semiconductor memory device according to the present invention reduces the chip area compared to the conventional semiconductor memory device using a pad.
Thus, the invention described herein makes possible the advantages of providing a semiconductor memory device which does not require the chip area to be increased even when the number of banks increases, and a method for producing such a semiconductor memory device.
This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.
REFERENCES:
patent: 4677742 (1987-07-01), Johnson
patent: 5384745 (1995-01-01), Konishi et al.
patent: 5387311 (1995-02-01), Hall et al.
patent: 5566128 (1996-10-01), Magome
Shioyama Kazutomo
Takata Hidekazu
Morrison & Foerster / LLP
Nelms David
Sharp Kabushiki Kaisha
Tran M.
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