Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
2000-06-08
2003-01-14
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
C138S097000, C138S097000
Reexamination Certificate
active
06506634
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor memory device of a redundant circuit system, and a method for producing the same.
2. Description of the Related Art
Semiconductor memory devices, particularly DRAMs, are scaled down and large-scale-integrated year by year. With such scale down and large scale integration, it become more and more difficult to hold the same yield as those of the last generation DRAMs. Therefore, in recent years, there is adopted a redundant circuit system for arranging a redundant cell array (an auxiliary cell array) for a memory array to substitute a redundant cell for a defective cell to carry out defect relief.
In a conventional redundant circuit technique, a fuse circuit capable of being cut (blown) by laser a is typically used as a defective address memory circuit. Specifically, a defective cell is identified by carrying out the die sort in the stage of a semiconductor wafer, on which a plurality of DRAM circuits have been integrated. On the basis of the defective address data, a corresponding fuse is cut by a laser blowing machine. Thereafter, the wafer is divided into DRAM chips, each of which is sealed in a package to carry out the final inspection thereof.
In the conventional redundant circuit technique using the laser blow, there are the following problems. First, if the scale of the DRAM increases by four, the scale of the fuse circuit for storing the defective address also increases by four, so that the throughput of the laser blow decreases to one-fourth. Secondly, since the pitch of the fuse array is determined by the capacity of the laser blowing machine, even if the DRAM has a fine design rule of 0.25 to 0.35 &mgr;m, the pitch of the fuse array can not be 3 to 4 &mgr;m or less. This means that the area occupied by the fuse array in the DRAM chip relatively increases every DRAM generation.
As a fuse element of a semiconductor integrated circuit other than the fuse element of the system capable of being cut by the laser blow, there are also known systems using an electric fuse capable of being electrically cut or short-circuited (e.g., see Japanese Patent Laid-Open No.
6-5707
and No.
6-302701
), and a system using a mechanical fuse capable of being cut by etching (e.g., Japanese Patent Laid-Open No.
1-308047
). If these fuses are used, the fuse array can be scaled down.
However, in a case where the electric fuse is used, if the scale of the fuse array becomes large, the scale of surrounding circuits, such as a signal generating circuit required for programming the fuse array, also becomes large. Therefore, there is some possibility that the area occupied by the defective address memory circuit including the fuse array and the surrounding circuits thereof is substantially equal to that when the fuse of the laser blow system is used. In addition, in a case where the mechanical fuse capable of being cut by etching is used, a programming step is carried out at least before a passivation step for a semiconductor wafer is completed, so that it is not possible to relieve a defective cell when the defective cell is produced at the subsequent step.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a semiconductor memory device capable of reducing the area occupied by a defective address memory circuit and surely carrying out defect relief, and a method for producing the same.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor memory device comprises: a memory cell array including memory cells arranged in the form of a matrix; a redundant cell array including redundant cells arranged for relieving a defective memory cell of the memory cell array; a defective address memory circuit including first and second memory circuits using different programming methods for storing an address of the defective memory cell of the memory cell array; and a substitution control circuit for controlling the substitution of one of the redundant cells of the redundant cell array for the defective memory cell of the memory cell array on the basis of memory data of the defective address memory circuit.
Preferably, the first memory circuit comprises a first fuse circuit including mechanical fuses capable of being cut by a reactive ion etching, and the second memory circuit comprises a second fuse circuit including electric fuses capable of being electrically cut or short-circuited.
The memory cell array may include a MOS transistor arranged on a semiconductor substrate, a capacitor connected to one of source and drain diffusion layers of the MOS transistor, and a signal wiring formed on the semiconductor substrate via an interlayer insulator film. In this case, the mechanical fuses of the first fuse circuit are preferably formed of the same wiring material film as that of the signal wiring of the memory cell array.
The signal wiring may have a multi-layer structure. In this case, the mechanical fuses of the first fuse circuit are preferably formed of the same material film as that of the uppermost layer wiring of the signal wiring.
Alternatively, when the memory cell array includes a MOS transistor arranged on a semiconductor substrate, a capacitor connected to one of source and drain diffusion layers of the MOS transistor, and a signal wiring formed on the semiconductor substrate via an interlayer insulator film, then the electric fuses of the second fuse circuit are preferably anti-fuses having a capacitor structure, which are formed of the same material as that of the capacitor of the memory cell array and which are formed at the same time that the capacitor of the memory cell array is formed.
Preferably, the first fuse circuit capable of being cut by the reactive ion etching has a larger scale than that of the second fuse circuit capable of being electrically cut or short-circuited.
According to another aspect of the present invention, a semiconductor memory device comprises: a memory cell array including memory cells arranged in the form of a matrix; a redundant cell array including redundant cells arranged for relieving a defective memory cell of the memory cell array; a defective address memory circuit including a memory circuit, which includes mechanical fuses capable of being cut by a reactive ion etching, for storing an address of the defective memory cell of the memory cell array; and a substitution control circuit for controlling the substitution of one of the redundant cells of the redundant cell array for the defective memory cell of the memory cell array on the basis of memory data of the defective address memory circuit.
According to a further aspect of the present invention, a method for producing a semiconductor memory device., comprises: a memory producing step of integrating and forming a memory circuit having a defective address memory circuit, which includes a first fuse circuit wherein mechanical fuses capable of being cut by a reactive ion etching are arranged, and a second fuse circuit wherein electrically fuses capable of electrically cut or short-circuited are arranged; a first programming step of carrying out a first defect analyzing test for the memory circuit and selectively cutting a corresponding fuse of the first fuse circuit by the reactive ion etching in accordance with the result of the first defect analyzing test; and a second programming step of carrying out a second defect analyzing test for the memory circuit and selectively cutting or short-circuiting a corresponding fuse of the second fuse circuit by applying an electric signal thereto in accordance with the result of the second defect analyzing test.
In this producing method, the first fuse circuit is preferably formed below a passivation film of a semiconductor wafer, on which the memory circuit is formed, and the first programming step is preferably carried out before forming the passivation film.
Preferably, the first programming step comprises the
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