Semiconductor memory device and method for operating the same

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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C365S194000

Reexamination Certificate

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07848178

ABSTRACT:
Semiconductor memory device and method for operating the same includes a phase detection unit configured to compare a phase of a first reference clock and a phase of a second divided reference clock to output a comparison result signal and a phase control and division unit configured to generate the second divided reference clock by dividing a second reference clock by a predetermined ratio according to the comparison result signal outputted from the phase detection unit and adjusting a phase of the second reference clock.

REFERENCES:
patent: 7450443 (2008-11-01), Cheng
patent: 2002/0196883 (2002-12-01), Best et al.
patent: 2000-124796 (2000-04-01), None

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