Static information storage and retrieval – Powering – Conservation of power
Reexamination Certificate
2003-12-31
2004-08-17
Young, Brian (Department: 2819)
Static information storage and retrieval
Powering
Conservation of power
C365S226000
Reexamination Certificate
active
06778460
ABSTRACT:
FIELD OF INVENTION
The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device and a core voltage generating method for stabilization of the core voltage during a refresh operation of the semiconductor memory device.
DESCRIPTION OF PRIOR ART
Generally, a semiconductor memory device is supplied with an external voltage VDD, and lowers a voltage level of the external voltage VDD to voltage levels of a core voltage VCORE and a peri voltage VPERI for operation of the semiconductor memory device; herein, the core voltage VCORE is used for reading data from a memory cell or writing data to the memory cell, and the peri voltage VPERI is used for operating internal circuits included in the semiconductor memory device.
Typically, in a conventional semiconductor memory device, a voltage level of the core voltage VCORE becomes unstable because excessive power consumption is occurred when a bit line is charged.
A core voltage generator raises the unstable core voltage VCORE to a stable voltage level. The core voltage generator determines whether or not the core voltage VCORE is stable by comparing the core voltage VCORE with a reference voltage VRC.
Herein, when the core voltage VCORE is unstable, an over driving controller is activated to drive the external voltage VDD over the core voltage VCORE.
RTOE and SBE are signals for the bit line charging. The conventional semiconductor memory device slows down activating speed of the RTOE and SBE to slow down power consuming speed of the core voltage VCORE during the bit line charging.
That is, the RTOE and SBE are activated to a logic ‘LOW’ level and to a logic ‘HIGH’ level respectively, and a predetermined time is needed to change levels of the RTOE and SBE. The semiconductor memory device extends the predetermined time so that the RTOE and SBE are activated slowly. Therefore, a voltage level of the core voltage VCORE is slowly downed.
FIG. 1
is a block diagram showing a power supply unit included in the conventional semiconductor memory device.
As shown, the conventional semiconductor memory device includes an over driving controller
11
, a core voltage generator
10
, a bit line sensing amplifier
12
and a bit line sensing amplifier controller
13
.
The over driving controller
11
receives a bit line sensing start signal SEST
30
and generates an over driving control signal SENSE_EN for driving an external voltage VDD over a core voltage VCORE. The core voltage generator
10
generates the core voltage VCORE for operating the bit line sensing amplifier
12
in response to the bit line sensing start signal SEST
30
and the over driving control signal SENSE_EN.
The bit line sensing amplifier
12
amplifies a potential difference between a bit line pair BL and BLB. The bit line sensing amplifier controller
13
generates a first enable signal RTOE and a second enable signal SBE. Herein, the first enable signal RTOE and the second enable signal SBE are for enabling a first activating voltage RTO (not shown) and a second activating voltage SB (not shown) each, where the first activating voltage RTO and the second activating voltage SB are for operating the bit line sensing amplifier
12
.
FIG. 2
is a circuit diagram showing the core voltage generator
10
shown in FIG.
1
.
As shown, the core voltage generator
10
includes a control unit
101
, a comparing unit
102
, a core voltage comparing operator
103
and an over driving unit
104
.
The control unit
101
turns on or off the comparing unit
102
depending on the bit line sensing start signal SEST
30
. The comparing unit
102
compares the reference voltage VRC with the core voltage VCORE to generate an enable signal COMP_EN depending on the comparison result. The over driving unit
104
generates the core voltage VCORE in response to the over driving control signal SENSE_EN.
The control unit
101
has an inverter I
3
, a PMOS transistor P
1
and NMOS transistors N
4
and N
5
.
Herein, the inverter I
3
inverts the bit line sensing start signal SEST
30
. An output of the inverter I
3
is connected to a gate of the PMOS transistor P
1
and a source of the P
1
is connected to an external voltage VDD. A gate of the NMOS transistor N
4
is connected to the output of the inverter I
3
, a drain of the N
4
is connected to a drain of the P
1
, a source of the N
4
is connected to a ground voltage VSS. A drain and a gate of the NMOS transistor N
5
are connected to the drain of the P
1
, a source of the N
5
is connected to the ground voltage VSS.
The comparing unit
102
has PMOS transistors P
2
, P
3
, P
4
and P
5
; and also has NMOS transistors N
1
, N
2
, N
3
, N
6
, N
7
, N
8
and N
9
.
Herein, the P
2
is paired with the P
3
constituting a differential amplifying unit, and the P
4
is paired with the P
5
also constituting the differential amplifying unit. The N
2
is controlled by the reference voltage VRC, and the N
3
is controlled by the core voltage VCORE. The N
2
and N
3
are input units for the differential amplifying unit. The N
7
severs as a current source for the differential amplifying unit. A gate of the N
1
is connected to the reference voltage VRC and a source of the N
1
is connected to a power voltage VDD. A gate of the N
6
is connected to the gate of the N
5
. The N
6
is connected between the drain of the N
1
and the ground voltage VSS. A gate of the N
8
is connected to the gate of the N
7
, and connected between the drain of the N
9
and the ground voltage VSS.
Herein, the gate of the N
3
is connected to the drain of the N
9
, and the gate of the N
2
is connected to the drain of the N
1
.
A gate of the P
6
included in the core voltage comparing operator
103
receives an enable signal COMP_EN. A source of the P
6
is connected to the power voltage VDD and a drain of the P
6
is connected to a gate of the N
9
.
A gate of the P
7
included in the over driving unit
104
receives the sense enable signal SENSE_EN. A source of the P
7
is connected to the power voltage VDD and a drain of the P
7
is connected to the gate of the N
9
.
FIGS. 3A and 3B
are circuit diagrams showing two different embodiments of the over driving controller
11
. A first embodiment shown in
FIG. 3A
is provided with a plurality of inverters. Meanwhile, a second embodiment shown in
FIG. 3B
is provided with a plurality of PMOS capacitors.
As described above, the over driving controller
11
generates the over driving control signal SENSE_EN for driving the power voltage VDD over the core voltage VCORE after the conventional semiconductor memory device is activated.
Referring to
FIG. 3A
, the over driving controller
11
includes inverters I
31
to I
37
and a NAND gate NAND
31
.
The inverters I
31
to I
37
invert and delay a bit line sensing start signal SEST
30
. The NAND gate NAND
31
receives the bit line sensing start signal SEST
30
and an outputted signal from the inverters I
31
to I
37
, and performs NAND operation on the two received signals, i.e., the bit line sensing start signal SEST
30
and the outputted signal from the inverters I
31
to I
37
.
Referring to
FIG. 3B
, the over driving controller
11
further includes inverters I
38
to I
43
, a NAND gate NAND
32
, an NMOS transistor N
31
and PMOS transistors P
31
to P
38
.
FIGS. 4A and 4B
are circuit diagrams showing the bit line sensing amplifier
12
.
FIG. 4A
shows a power supplying unit of the bit line sensing amplifier
12
, and
FIG. 4B
shows an amplifying unit of the bit line sensing amplifier
12
.
Referring to
FIG. 4A
, the power supplying unit of the bit line sensing amplifier
12
includes a first supplying unit
40
and a second supplying unit
41
.
Herein, a first activating voltage RTO is supplied power by the core voltage VCORE or the power voltage VDD in response to first enable signal RTOE. A second activating voltage SB is supplied power by the ground voltage VSS in response to a second enable signal SBE.
The first supplying unit
40
is formed by a PMOS transistor P
41
; herein, a gate of the P
41
is connected to the first enable s
Blakely , Sokoloff, Taylor & Zafman LLP
Hynix / Semiconductor Inc.
Nguyen John B
Young Brian
LandOfFree
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