Semiconductor memory device and method for generating output...

Details Semiconductor memory device and method for generating output... Semiconductor memory device and method for generating output...

2011-05-17

2011-05-17

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S191000, C365S193000, C365S194000, C365S233110, C365S233120

Reexamination Certificate

active

07944772

ABSTRACT:
A semiconductor memory device includes a DLL for detecting a phase difference between an external clock signal and a feedback clock signal to generate a delay control signal corresponding to the phase difference, and delaying the external clock signal by a delay amount corresponding to the delay control signal to generate a DLL clock signal; a clock counter reset signal generator for synchronizing an output enable reset signal with the external clock signal, delaying the synchronized signal by a delay amount corresponding to the delay control signal, and latching the delayed signal in response to the DLL clock signal to output a clock counter reset signal; and an output enable signal generator, reset in response to the clock counter reset signal, for counting the external clock signal and the DLL clock signal to generate an output enable signal corresponding to a read command and a CAS latency.

REFERENCES:
patent: 7511546 (2009-03-01), Koo
patent: 7561490 (2009-07-01), Kim et al.
patent: 7672191 (2010-03-01), Jang
patent: 1020050041584 (2005-05-01), None
patent: 1020070056505 (2007-06-01), None
Notice of Allowance issued from Korean Intellectual Property Office on Sep. 27, 2010.

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