Static information storage and retrieval – Format or disposition of elements
Patent
1999-11-12
2000-07-11
Nelms, David
Static information storage and retrieval
Format or disposition of elements
365 63, 36523008, G11C 502
Patent
active
060882530
ABSTRACT:
A synchronous DRAM has a plurality of data pads formed into a data pad row, a plurality of data latch circuits for latching signals from each of the data pads, these data latch circuits being disposed in a region surrounded by a second straight line that is perpendicular to a first straight line that passes over the data pad row and that passes one end of the data pad row, and a third straight line that is parallel to the second straight line and that passes the other end of the data pad row. The length of interconnections from the plurality of data latch circuits to an internal clock signal generating circuit being made the same length, the length of the interconnection between each first stage circuit to each data latch circuit being made the same as the length of the interconnection from the internal clock signal generating circuit to the data latch circuits, and the first stage circuits, the data latch circuits, and the internal clock signal generating circuit being operated by a voltage that is dropped down from an external power supply.
REFERENCES:
patent: 5122693 (1992-06-01), Honda et al.
patent: 5376842 (1994-12-01), Honoa et al.
patent: 6005412 (1999-12-01), Ranjan et al.
Le Thong
NEC Corporation
Nelms David
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