Semiconductor memory device and method for fabricating the same

Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating

Reexamination Certificate

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C257SE29264, C257SE29309

Reexamination Certificate

active

07851892

ABSTRACT:
A semiconductor memory device has a substrate having a semiconductor layer, an n-type semiconductor region formed beneath a main surface of the semiconductor layer, a plurality of cell gates being aligned at a space from each other and including a gate insulating film formed on the main surface of the semiconductor layer, a charge storage layer formed on the gate insulating film, a charge block layer formed on the charge storage layer and a control gate electrode formed on the charge block layer, an insulating film between cells formed on the main surface of the semiconductor layer between the cell gates, and a carbon accumulation region formed in the insulating film between the cells and has a maximum concentration of a carbon element in a region within 2 nm from an interface between the semiconductor layer and the insulating film between the cells.

REFERENCES:
patent: 2001/0034135 (2001-10-01), Miyakawa
patent: 2006/0237706 (2006-10-01), Enda et al.
patent: 2006/0240619 (2006-10-01), Ozawa et al.
patent: 2006/0267067 (2006-11-01), Ishihara
patent: 2007/0054453 (2007-03-01), Buh et al.
patent: 2007/0080390 (2007-04-01), Geissler et al.
patent: 2006-294711 (2006-10-01), None
patent: 2006-310393 (2006-11-01), None
Depas et al., “Definition of dielectric breakdown for ultra thin (< 2 nm) gate oxides”, 1997, Solid-State Electronics, vol. 41, No. 4, pp. 725-728.

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