Semiconductor memory device and method for erasing the same

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185170, C365S185180, C365S185290, C365S185300

Reexamination Certificate

active

07974130

ABSTRACT:
A semiconductor memory device including a memory cell array with NAND cell units arranged therein, the NAND cell unit having a plurality of electrically rewritable and non-volatile memory cells connected in series, first and second select gate transistors disposed for coupling the both ends of the NAND cell unit to a bit line and a source line, respectively, and a dummy cell disposed adjacent to at least one of the first and second select gate transistors, wherein after erasing the memory cells in an erase unit, the memory cells excepting the dummy cell are subject to soft-program.

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patent: 7480178 (2009-01-01), Park et al.
patent: 7619930 (2009-11-01), Mokhlesi
patent: 2006-186359 (2006-07-01), None
patent: 1993-0009064 (1993-05-01), None
patent: 10-2006-0110755 (2006-10-01), None
patent: WO 2006/025089 (2006-03-01), None

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