Semiconductor memory device and method for driving...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185160, C365S185170, C365S063000, C365S072000

Reexamination Certificate

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08072806

ABSTRACT:
A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors.

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patent: 2002/0018374 (2002-02-01), Takeda et al.
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patent: 5-198190 (1993-08-01), None
patent: 9-213094 (1997-08-01), None
patent: 11-330426 (1999-11-01), None

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