Semiconductor memory device and method for accessing memory...

Details Semiconductor memory device and method for accessing memory... Semiconductor memory device and method for accessing memory...

2001-07-23

2002-07-23

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189110, C365S204000

Reexamination Certificate

active

06424589

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a semiconductor memory device and more particularly to circuitry for selecting a word line in a memory cell array.
BACKGROUND OF THE INVENTION
In semiconductor devices, increased integration and improved processing techniques have improved operating speeds. As operating speeds of a central processing unit (CPU) increases, it becomes desirable to reduce the time required for reading and writing data to a memory cell of a semiconductor memory device.
A boosted potential can be applied to a word line in order to write, read, or refresh data in a memory cell. This can improve operational speeds by increasing the data signal stored in a memory cell by increasing the amount of charge that can be stored on a storage capacitor. The boosted potential may also increase speeds by decreasing the resistance of a memory cell transistor.
When reading or writing is finished, the potential on the word line is lowered (typically to a ground potential). In order to improve speeds, it is desirable to discharge the word line as quickly as possible, so that a precharge operation can be more quickly executed. This can decrease the memory cell access cycle time.
Referring now to
FIG. 1
, a block schematic diagram of a conventional DRAM is shown and given the general reference character
10
.
Conventional DRAM
10
includes four memory banks (B
1
to B
4
), main word decoders (XDEC
1
to XDEC
4
), RA drivers (RAD
1
to RAD
5
), and sub-word drivers (SWD
1
to SWD
20
).
Main word decoders (XDEC
1
to XDEC
4
) receive row addresses (X
2
to Xj) and provide main word lines MWL. For example, main word decoder XDEC
1
provides main word lines (MWL
00
to MWL
0
i
). Main word decoder XDEC
2
provides main word lines (MWL
10
to MWL
1
i
). Main word decoder XDEC
3
provides main word lines (MWL
20
to MWL
2
i
). Main word decoder XDEC
4
provides main word lines (MWL
30
to MWL
3
i
).
A main word line MWL from one of main word decoders (XDEC
1
to XDEC
4
) is selected based on the value of row addresses (X
2
to Xj). When selected, a main word line MWL transitions to a high level.
RA drivers (RAD
1
to RAD
5
) receive row addresses (X
0
and X
1
) and control signal RAE and generate sub-word select signals (RA
00
to RA
42
). Sub-word select signals are received by sub-word drivers (SWD
1
to SWD
20
). Sub-word drivers (SWD
1
to SWD
20
) then select a sub-word line (not shown in
FIG. 1
) in each bank (B
1
to B
4
) based on the selected main word line MWL and sub-word select signals (RA
00
to RA
42
) selected.
Each memory bank (B
1
to B
4
) includes four cell arrays (CELL
0
to CELL
15
) and five sense amplifier rows (SA
0
to SA
19
). Bank B
1
includes cell arrays (CELL
0
to CELL
3
) and sense amplifier rows (SA
0
to SA
4
). Bank B
2
includes cell arrays (CELL
4
to CELL
7
) and sense amplifier rows (SA
5
to SA
9
). Bank B
3
includes cell arrays (CELL
8
to CELL
11
) and sense amplifier rows (SA
10
to SA
14
). Bank B
4
includes cell arrays (CELL
12
to CELL
15
) and sense amplifier rows (SA
15
to SA
19
).
When receiving a high sub-word select signal (RA
00
to RA
42
) and a high main word line MWL, a sub-word driver (SWD
1
to SWD
20
) selects a sub-word line (not shown) in an adjacent cell array, such that a cell array in each bank has an active sub-word line during an activation cycle.
Sub-word drivers (SWD
5
to SWD
16
) select a sub-word line in two adjacent cell arrays. For example, sub-word driver SWD
5
selects a sub-word line in both cell array (CELL
0
and CELL
4
) when one of main word lines (MWL
00
to MWL
0
i
) is high (activated) and one of RA signals (RA
11
and RA
13
) is high (activated).
Sub-word drivers (SWD
1
to SWD
20
) include end sub-word drivers (SWD
1
to SWD
4
and SWD
17
to SWD
20
) that select a sub-word line in the adjacent end cell array. For example, sub-word driver SWD
1
selects a sub-word line in cell array CELL
0
when one of main word lines (MWL
00
to MWL
0
i
) is high (activated) and one of RA signals (RA
00
and RA
02
) is high (activated).
When row addresses (X
1
and X
0
) have the value {low, low} respectively, RA signals (RA
00
, RA
20
, and RA
40
) become high, while other RA signals remain low. Assuming, main word decoder XDEC
1
has received a row address (X
2
to Xj) that activates one of main word lines (MWL
00
to MWL
0
i
), a sub-word line in cell array CELL
0
is activated by sub-word decoder SWD
1
, a sub-word line in cell arrays (CELL
4
and CELL
8
) is activated by sub-word decoder SWD
9
, and a sub-word line in cell array CELL
12
is activated by sub-word decoder SWD
17
.
When row addresses (X
1
and X
0
) have the value {low, high} respectively, RA signals (RA
11
and RA
31
) become high, while other RA signals remain low. Assuming, main word decoder XDEC
1
has received a row address (X
2
to Xj) that activates one of main word lines (MWL
00
to MWL
0
i
), a sub-word line in cell arrays (CELL
0
and CELL
4
) is activated by sub-word decoder SWD
5
, and a sub-word line in cell arrays (CELL
8
and CELL
12
) is activated by sub-word decoder SWD
13
.
When row addresses (X
1
and X
0
) have the value {high, low} respectively, RA signals (RA
02
, RA
22
, and RA
42
) become high, while other RA signals remain low. Assuming, main word decoder XDEC
1
has received a row address (X
2
to Xj) that activates one of main word lines (MWL
00
to MWL
0
i
), a sub-word line in cell array CELL
0
is activated by sub-word decoder SWD
1
, a sub-word line in cell arrays (CELL
4
and CELL
8
) is activated by sub-word decoder SWD
9
, and a sub-word line in cell array CELL
12
is activated by sub-word decoder SWD
17
.
When row addresses (X
1
and X
0
) have the value {high, high} respectively, RA signals (RA
13
and RA
33
) become high, while other RA signals remain low. Assuming, main word decoder XDEC
1
has received a row address (X
2
to Xj) that activates one of main word lines (MWL
00
to MWL
0
i
), a sub-word line in cell arrays (CELL
0
and CELL
4
) is activated by sub-word decoder SWD
5
, and a sub-word line in cell arrays (CELL
8
and CELL
12
) is activated by sub-word decoder SWD
13
.
In this way, one cell array (CELL
0
to CELL
15
) is selected in each bank (B
1
to B
4
). Sense amplifier rows (SA
0
to SA
19
) adjacent to selected banks detect data values stored in memory cells connected to the selected sub-word lines. For example, if cell arrays (CELL
0
, CELL
4
, CELL
8
, and CELL
12
) are selected, respective adjacent sense amplifier rows will sense the data values in the selected memory cells. Sense amplifier rows (SA
0
and SA
1
) sense data from cell array CELL
0
. Sense amplifier rows (SA
5
and SA
6
) sense data from cell array CELL
4
. Sense amplifier rows (SA
10
and SA
11
) sense data from cell array CELL
8
. Sense amplifier rows (SA
15
and SA
16
) sense data from cell array CELL
12
.
Although in
FIG. 1
, RA drivers (RAD
1
to RAD
5
) are shown to output RA signals (RA
00
to RA
42
), complementary RA signals (RAB
00
to RAB
42
) are also generated, but not shown to avoid unduly cluttering the figure.
Referring now to
FIG. 2
, a block schematic diagram of a portion of conventional DRAM
10
is set forth.
The portion of conventional DRAM
10
includes a portion of cell array CELL
0
, sub-word decoders (SWD
1
and SWD
5
), and sense amplifier rows (SA
0
and SA
1
).
Each sub-word decoder (SWD
1
and SWD
5
) includes a plurality of sub-decoder blocks SB. For example, sub-word decoder SWD
1
includes sub-decoder blocks (SB
0000
to SB
0
i
02
). RA-drivers (RAD
1
and RAD
2
) generate RA signals (RA
00
to RA
03
) that select predetermined sub-decoder blocks SB.
Cell array CELL
0
includes a plurality of memory cells arranged in rows and columns. Each memory cell is connected to receive a sub-word line SWL. Each memory cell is connected to a bit line BT. Two examples of memory cells are illustrated as memory cells (M
1
and M
2
) which are connected to sub-word line SWL
0000
. Memory cells (M
1
and M
2
) include a memory cell transistor an

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