Semiconductor memory device and memory system

Details Semiconductor memory device and memory system Semiconductor memory device and memory system

1996-04-26

1998-10-06

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523001, 36518901, 365229, 36518905, H01L 2710

Patent

active

058187847

ABSTRACT:
Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.

REFERENCES:
patent: 5499213 (1996-03-01), Niimi et al.
H. Yamauchi et al., "FA 14.1: A Sub-0.5.mu. A/MB Data-Retention DRAM", 1995 IEEE International Solid-State Circuits Conference, pp. 244-249.

Affiliated with

Also associated with

Rating

Semiconductor memory device and memory system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device and memory system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device and memory system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-86574