Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Patent
1996-01-24
1997-11-25
Fears, Terrell W.
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
365200, G11C 1300
Patent
active
056919522
ABSTRACT:
Input/output terminals of a first semiconductor memory device in which failures or defects exist in units of memory mats and input/output terminals of a second semiconductor memory device having redundant memory mats are connected to one another on a mounted substrate to thereby relieve the failures in the memory mat units. A power source is substantially cut off from supplying to a faulty memory mat.
REFERENCES:
patent: 4688219 (1987-08-01), Takemae
patent: 5193071 (1993-03-01), Umina et al.
patent: 5262993 (1993-11-01), Horiguchi et al.
Aoki Masakazu
Horiguchi Masashi
Inoue Kiyoshi
Sasaki Toshio
Sugano Toshio
Fears Terrell W.
Hitachi , Ltd.
Hitachi Tohbu Semiconductor, Ltd.
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