Semiconductor memory device and manufacturing method thereof

Details Semiconductor memory device and manufacturing method thereof Semiconductor memory device and manufacturing method thereof

2011-07-19

2011-07-19

Mandala, Victor (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

C257S202000, C257S211000, C257SE27081, C257SE29170, C257SE29119

Reexamination Certificate

active

07982244

ABSTRACT:
A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.

REFERENCES:
patent: 6376876 (2002-04-01), Shin et al.
patent: 6943453 (2005-09-01), Goda et al.
patent: 6974979 (2005-12-01), Watanabe et al.
patent: 2005/0218460 (2005-10-01), Hasegawa et al.
patent: 2006/0065913 (2006-03-01), Sakuma et al.
patent: 2007/0002622 (2007-01-01), Matsunaga et al.
patent: 2008/0239799 (2008-10-01), Watanabe
patent: 2008/0293201 (2008-11-01), Goda et al.
patent: 2003-188252 (2003-07-01), None

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