Semiconductor memory device and its testing method

Details Semiconductor memory device and its testing method Semiconductor memory device and its testing method

2005-05-03

2005-05-03

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S201000, C365S194000, C365S206000

Reexamination Certificate

active

06888774

ABSTRACT:
A semiconductor memory device is of a bank switching type having a plurality of memory array banks provided in a memory chip which can be switched from one to another for storage operation. The semiconductor memory device includes: a plurality of memory arrays in the memory array banks; an input/output circuit for transmitting information data between the memory arrays and the outside; a data bus for connecting between the memory arrays and the input/output circuit; and N-channel transistors provided across the data bus. The data bus consists of a plurality of adjacent lines. Each of N-channel transistors is connected at their drain to the corresponding lines of the data bus while at their source to the ground. When a multi-bit test is commenced for writing and reading data on the memory arrays, the N-channel transistors are turned on to connect the lines of the data bus to the ground.

REFERENCES:
patent: 4821232 (1989-04-01), Nakano et al.
patent: 5917758 (1999-06-01), Keeth

Affiliated with

Also associated with

Rating

Semiconductor memory device and its testing method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device and its testing method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device and its testing method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3401411