Semiconductor memory device and information processing system

Details Semiconductor memory device and information processing system Semiconductor memory device and information processing system

2002-08-26

2004-12-07

Lam, David (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189011, C365S189120

Reexamination Certificate

active

06829195

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a semiconductor memory device and an information processing system, and more particularly, to techniques of shortening the operation cycle time of a semiconductor memory device and an information processing system.
(2) Description of the Related Art
A semiconductor memory device and a control device for controlling the memory device exchange data with each other in blocks of bits whose number is determined, for example, by an application such as an OS (Operating System).
In the case of an application wherein the number of bits transferred as one block is small, increase in the quantity of read/write data entails a correspondingly large number of command entries. Accordingly, auto-precharge type DRAM (Dynamic Random Access Memory) which performs read operation and precharge operation at the same time in response to a single entry of command, SRAM (Static RAM) which requires no precharge operation, etc. are useful for the purpose.
This will be explained with reference to
FIGS. 22 and 23
.
FIGS.
22
(A),
22
(B) and
22
(C) illustrate the operation of a DRAM with no auto-precharge function, that is, a non-auto-precharge type DRAM wherein the number of data bits read out at a time is two. In the case of the non-auto-precharge type DRAM, a precharge command (PRE
1
-PRE
3
) needs to be entered following the access in order to execute precharge operation, as shown in FIG.
22
(B). In the illustrated example, read commands (RD
1
-RD
3
) are input respectively at the leading edges of the zeroth, second and fourth basic clock pulses (FIG.
22
(A)), and precharge commands (PRE
1
-PRE
3
) are input respectively at the leading edges of the first, third and fifth clock pulses. As a result of the entry of the read commands, 2-bit blocks of data (Q
11
, Q
12
; Q
21
, Q
22
; Q
31
, Q
32
) are output from a DATA output terminal at the leading edges of the first, third and fifth clock pulses, respectively, as shown in FIG.
22
(C).
FIGS.
23
(A),
23
(B) and
23
(C) illustrate the operation of an auto-precharge type DRAM capable of automatic precharge operation wherein the number of data bits read out at a time is two. As shown in the figures, in the case of the auto-precharge type DRAM, no precharge command needs to be entered, so that the read commands (RD
1
-RD
3
) can be continuously input, as seen from FIG.
23
(B). Also, since the interval between commands can be shortened, the interval between data (Q
11
, Q
12
, Q
21
, Q
22
, Q
31
, Q
32
) output from the DATA output terminal is shorter than in the case of
FIG. 22
, as seen from FIG.
23
(C). Compared with the case shown in
FIG. 22
, therefore, all data can be read out in a shorter period of time.
As explained above, where the number of data bits exchanged between the semiconductor memory device and the control device therefor is small, a device capable of automatic precharge operation, like the auto-precharge type DRAM, is useful because it ensures relatively high density of commands and as a consequence, higher data access density.
The foregoing explains the case where the number of data bits exchanged between the semiconductor memory device and the control device therefor is small; in the following will be considered a case where the number of bits is large.
FIGS.
24
(A),
24
(B) and
24
(C) illustrate the operation of an auto-precharge type DRAM wherein the number of data bits exchanged with the control device is eight. In the illustrated example, a read command RD
1
(FIG.
24
(B)) is input at the leading edge of the zeroth basic clock pulse shown in FIG.
24
(A), and as a result, readout data is output from the DATA output terminal, as shown in FIG.
24
(C).
FIGS.
25
(A),
25
(B) and
25
(C) illustrate the operation of an auto-precharge type DRAM wherein the number of data bits exchanged with the control device is eight and the number of data bits read out at a time is two.
As shown in the figures, in the case where a DRAM from which two bits of data can be read out at a time is applied to a system in which the number of data bits exchanged with the control device is eight, four RD commands (RD
1
-RD
4
) need to be input. Since, as a result, the interval between the RD commands becomes shorter, an inconvenience arises in that during the access other devices are unable to access the DRAM.
There have also been proposed semiconductor memory devices in Unexamined Japanese Patent Publications (KOKAI) Nos. 2-94194 and 7-192458, wherein at the time of write operation, identical data is written into a plurality of memory banks and at the time of read operation, data is sequentially read out from different memory banks, to thereby shorten the random access time during the read operation.
FIG. 26
illustrates the operation of a clock synchronization type, among semiconductor memory devices of this type. The semiconductor memory device has four memory banks BANK
0
to BANK
3
for holding identical data.
FIG. 26
exemplifies a case where a write cycle intervenes between read cycles.
Read commands RD
1
to RD
6
are sequentially supplied in synchronism with a clock signal CLK ((a) in FIG.
26
). In response to the read commands RD
1
to RD
6
, the four memory banks BANK
0
to BANK
3
operate in turn ((b) in FIG.
26
), so that readout data Q
1
to Q
6
are output in succession ((c) in FIG.
26
). In the illustrated example, the read operation period of each of the memory banks BANK
0
to BANK
3
is four clock cycles, but since the memory banks BANK
0
to BANK
3
operate in parallel, the read cycle corresponds to one clock cycle.
Following the read command RD
6
, a write command WR
7
is supplied ((d) in FIG.
26
). In response to the write command WR
7
, all of the memory banks BANK
0
to BANK
3
perform write operation at the same time. Accordingly, the write command WR
7
is supplied after all of the memory banks BANK
0
to BANK
3
have become idle. In the illustrated example, the write command WR
7
needs to be supplied after completion of the operation of the memory bank BANK
1
. Consequently, a READ-WRITE interval (timing specification) from the supply of the read command RD
6
to the supply of the write command WR
7
is four clock cycles equal to the operation period of the memory bank BANK
1
.
In response to the write command WR
7
, the four memory banks BANK
0
to BANK
3
perform the write operation at the same time, and as a result, identical write data D
7
is written into the memory banks BANK
0
to BANK
3
((e) in FIG.
26
). Since the identical write data D
7
is written in the four memory banks BANK
0
to BANK
3
at the same time, the write cycle is equal to four clock cycles corresponding to the write operation period of the memory banks BANK
0
to BANK
3
.
Subsequently, read commands RD
8
to RD
11
are sequentially supplied ((f) in FIG.
26
). The four memory banks BANK
0
to BANK
3
operate in turn ((g) in
FIG. 26
) and readout data Q
8
to Q
11
are output in succession ((h) in
FIG. 26
) in the same manner as described above.
Conventionally, an optimum device must be selected in accordance with the number of data bits exchanged between the semiconductor memory device and the control device therefor, as seen from
FIGS. 22
to
25
. In other words, there was no conventional device that can cope with all probable numbers of bits.
Also, as shown in
FIG. 26
, all of the memory banks BANK
0
to BANK
3
perform write operation at the same time. Accordingly, in cases where a write cycle intervenes between read cycles, the write command WR
7
needs to be supplied after the read operations of all memory banks BANK
0
to BANK
3
are completed. As a result, the supply of the write command WR
7
must be deferred for four clock cycles after the supply of the read command RD
6
. Further, the interval (READ-READ command interval) required from the read command RD
6
to the next read command RD
8
corresponds to the sum of the operation period of the memory bank BANK
1
which is the last to perform the read operation and the write operation peri

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