Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2002-11-14
2004-07-20
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S063000, C365S230010, C365S185110, C365S185130, C365S230060
Reexamination Certificate
active
06765841
ABSTRACT:
Japanese Patent Application No. 2001-349263, filed on Nov. 14, 2001, is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device such as an SRAM and an electronic instrument using the same. More particularly, the present invention relates to a semiconductor memory device capable of achieving an increase in the degree of integration and an increase in speed, and an electronic instrument using the same. In more detail, the present invention relates to improvement for driving a sub word line at high speed.
In this type of semiconductor memory device, an increase in the degree of integration and an increase in speed have been demanded. The number of memory cells is increased in the vertical direction and the horizontal direction if the degree of integration is increased.
If the number of memory cells in the horizontal direction is increased, the number of memory cells directly connected with one word line is increased. This results in an increase in load resistance and load capacitance of one word line, whereby the word line cannot be selectively driven at high speed.
Therefore, the memory cell array is divided into blocks in the horizontal direction and a plurality of main word lines is disposed across a plurality of memory blocks. A plurality of sub word lines subordinate to each of the plurality of main word lines is disposed in each of the plurality of memory blocks. The load capacitance of one main word line is decreased in this manner.
If the number of memory cells in the vertical direction is increased, it is difficult to selectively drive the sub word line at high speed. A plurality of sub word select signal lines for selecting one of the plurality of sub word lines in each memory block is disposed along the vertical direction. If the number of memory cells is increased in the vertical direction, the length of the plurality of sub word select signal lines is increased in the vertical direction, whereby load resistance and load capacitance are increased. Therefore, it is difficult to selectively drive the sub word line at high speed due to rounding of the waveform of sub word select signals supplied to the plurality of sub word select signal lines.
BRIEF SUMMARY OF THE INVENTION
The present invention may provide a semiconductor memory device enabling high integration and high speed, and an electronic instrument using the same.
The present invention may also provide a semiconductor memory device which enables a sub word line to be selectively driven at high speed by decreasing waveform rounding of a sub word select signal supplied to a sub word select signal line. and an electronic instrument using the same.
One aspect of the present invention provides a semiconductor memory device comprising:
a memory cell array;
a plurality of main word lines extending along a first direction in the memory cell array;
a row decoder which selects one of the main word lines;
a plurality of memory blocks formed by dividing the memory cell array in a first direction;
a plurality of sub word lines disposed in each of the plurality of memory blocks and subordinate to each of the main word lines;
a plurality of sub row decoders respectively provided for the memory blocks, each of the sub row decoders having a plurality of sub word select signal lines extending along a second direction which intersects the first direction to select one of the sub word lines;
a first signal supply section which is disposed on one end in the second direction and supplies a plurality of sub word select signals to the sub word select signal lines in each of the sub row decoders; and
a second signal supply section which is disposed on the other end in the second direction and supplies the sub word select signals to the sub word select signal lines in each of the sub row decoders.
According to this aspect of the present invention, the sub word select signals at an active potential are supplied from the first signal supply section connected to one end of the sub word select signal lines and the second signal supply section connected with the other end of the sub word select signal lines. Therefore, even if load capacitance and load resistance of the sub word select signal lines are increased by an increase in the degree of integration, charging or discharging until the sub word select signal lines reach the active potential is not delayed.
According to another aspect of the present invention, there is provided an electronic instrument comprising the above semiconductor memory device. The performance of the electronic instrument is improved by having such a highly-integrated semiconductor memory device capable of operating at high speed.
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