Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2003-02-07
2004-10-19
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S042000, C365S230010, C365S230060, C365S230080
Reexamination Certificate
active
06807126
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device used for an electronic information device such as a cellular phone, for example, a flash memory, and an electronic information device using such a semiconductor memory device.
2. Description of the Related Art
Conventionally, a flash memory performs a memory operation such as data write or data erase by controlling an operation of raising or lowering an internal voltage and an operation of applying a pulse voltage for writing information to a memory cell or a pulse voltage for erasing information from a memory cell. Such a control is performed in synchronization with an internal clock signal generated in a control circuit.
FIG. 9
is a block diagram illustrating a partial structure of a conventional general flash memory.
As shown in
FIG. 9
, the flash memory includes a memory array
11
having a plurality of memory cells (not shown) arranged in a row direction and a column direction. The memory cells are provided at intersections of a plurality of word lines (not shown) arranged in the row direction and a plurality of bit lines (not shown) arranged in the column direction. Each memory cell is connected to a word line and a bit line crossing each other in the vicinity of the memory cell. The memory array
11
includes an X decoder
11
a
for selecting a word line among the plurality of word lines, and a Y decoder
11
b
for selecting a bit line among the plurality of bit lines. The X decoder
11
a
and the Y decoder
11
b
each receive an address from an address pad
12
via an input buffer
13
, an address counter
14
and an address multiplexer
15
. In accordance with the address, a word line and a bit line are selected by the X decoder
11
a
and the Y decoder
11
b
. To the memory cell connected to the selected word line and bit line, data which is input from an I/O pad
16
via an input buffer
17
and a data register
18
is written. Data which is written to the memory cell is output from the Y decoder
11
b
to the I/O pad
16
via an output multiplexer
19
and an output buffer
20
.
The input buffer
13
connected to the address pad
12
, and the input buffer
17
and the output pad
20
connected to the I/O pad
16
, are controlled by an input/output logic
21
.
The input/output logic
21
receives control signals such as, for example, /CE, /WE, /OE and /RP which are supplied from an external CPU. The input buffer
13
, the input buffer
17
and the output buffer
20
are controlled by the control signals. By such control, an address which is input from the address pad
12
is temporarily stored in the input buffer
13
, data which is input from the I/O pad
16
is temporarily stored in the input buffer
17
, and data which is output to the I/O pad
16
is temporarily stored in the output buffer
20
.
A command user interface
22
receives and then decodes a command. In accordance with the decoding result, the command user interface
22
performs controlling operations of, for example, (1) setting or resetting data in a status register
23
, (2) switching the output multiplexer
19
to supply the output buffer
20
with data which is read from the memory array
11
and output from the Y decoder
11
b
or to supply the output buffer
20
with status data in the status register
23
, (3) storing data input from the I/O pad
16
in the data register
18
. The command which is input to the command user interface
22
is output to a write state machine
24
.
When the command is input to the write state machine
24
from the command user interface
22
, the write state machine
24
generates a control signal for controlling an operation of writing data which is input from the I/O pad
16
to the memory cell or erasing data from the memory cell (hereinafter, referred to as an “internal control signal”). The internal control signal generated by the write state machine
24
is supplied to an internal voltage generation circuit
25
. In accordance with the internal control signal, a controlling operation of, for example, generating an internal voltage necessary to write or erase data or stopping the generation of the internal voltage, is performed. The internal control signal is also supplied to a data comparator
26
which receives data from the Y decoder
11
b
. In accordance with the internal control signal, the data comparator
26
for verifying data is controlled to be on or off when the data is written or erased. The internal control signal is also supplied to the address counter
14
and the address multiplexer
15
which receive an address input to the address pad
12
via the input buffer
13
. When the data is erased, the address of the memory cell, the data in which is verified, is changed by the address counter
14
and the address multiplexer
15
.
The internal voltage generation circuit
25
includes a voltage raising circuit for raising an externally input supply voltage so as to generate an internal voltage which is necessary to write or erase data, and a voltage dropping circuit for dropping the raised voltage. When an internal control signal for activating the internal voltage generation circuit
25
(activation signal) is input thereto from the write state machine
24
, an operation of raising the internal voltage by the voltage raising circuit or an operation of dropping the internal voltage by the voltage dropping circuit is started. When an internal control signal for deactivating the internal voltage generation circuit
25
(deactivation signal) is input thereto from the write state machine
24
, an operation of raising the internal voltage by the voltage raising circuit or an operation of dropping the internal voltage by the voltage dropping circuit is stopped.
With the flash memory having the above-described structure, an operation of writing data to a memory cell or erasing data from a memory cell is performed in the following manner. First, a command instructing the flash memory to, for example, write data or erase data is issued from an external CPU. When the command is input to the flash memory, the command is decoded by the write state machine
24
and a necessary internal control signal is generated in accordance with the decoding result. The internal control signal controls functional blocks in the flash memory so as to execute the operation instructed by the command.
FIG. 10
is a block diagram illustrating a partial structure of the write state machine
24
shown in FIG.
9
.
As shown in
FIG. 10
, the write state machine
24
includes a processing circuit
101
for executing various types of processing, a control code generation circuit
102
for supplying the processing circuit
101
with a control code, an internal clock generation circuit
103
for supplying the processing circuit
101
with a timing signal (internal clock signal), and a plurality of latch registers A through F connected to the processing circuit
101
.
The control code generation circuit
102
has a built-in control code (microcode) describing an algorithm used for executing the operation instructed by the command. When the command is input to the flash memory and the, instruction of the command is given to the control code generation circuit
102
, the control code corresponding to the command is supplied from the control code generation circuit
102
to the processing circuit
101
. In a flash memory, algorithms used for, for example, switching the voltage raising circuit or the voltage dropping circuit into an active state or an inactive state, or applying a prescribed write pulse voltage to a gate, a source and a drain of a memory cell to write data to the memory cell, are built into the control code generation circuit
102
as control codes.
The internal clock generation circuit
103
generates the internal clock signal and supplies the internal clock signal to the processing circuit
101
.
The processing circuit
101
sequentially decodes the control codes in synchronization with the internal clock signal generated by the internal clock generation c
Luu Pho M.
Morrison & Foerster / LLP
Nguyen Van Thu
Sharp Kabushiki Kaisha
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