Semiconductor memory device and electric device with the same

Details Semiconductor memory device and electric device with the same Semiconductor memory device and electric device with the same

2006-12-19

2006-12-19

Tran, Michael (Department: 2827)

Static information storage and retrieval

Read only systems

Resistive

C365S230060

Reexamination Certificate

active

07151686

ABSTRACT:
A semiconductor memory device having: a cell array including bit lines, word lines and memory cells disposed at crossings thereof, plural memory cells being connected in series to constitute a NAND cell unit, plural blocks being arranged, each being constituted by plural NAND cell units arranged in the word line direction; and a row decoder configured to select a block, wherein the row decoder includes: transferring transistor arrays disposed in association with the blocks, in each of which transistors are arranged for transferring word line drive voltages; first decode portions disposed in association with the transferring transistor arrays, which are applied with boosted voltages to selectively drive the transferring transistor arrays; and second decode portions configured to select one of the blocks, each of which is disposed to be shared by adjacent two first decode portions.

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patent: 2000-76880 (2000-03-01), None
patent: 2002-0023501 (2002-03-01), None
Patent Abstracts of Japan, JP 2002-280463, Sep. 27, 2002 (with corr. US 6,720,612).

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