Semiconductor memory device and electric device with the same

Details Semiconductor memory device and electric device with the same Semiconductor memory device and electric device with the same

2005-12-20

2005-12-20

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185200, C365S185230

Reexamination Certificate

active

06977845

ABSTRACT:
A semiconductor memory device includes: a plurality of cell array blocks in each of which a plurality of memory cells are arranged; address decode circuits for selecting memory cells in the cell array blocks; sense amplifier circuits for reading cell data of the cell array blocks; and a busy signal generation circuit for generating a busy signal to the chip external, wherein in a first read cycle selecting a first area in a first cell array block, cell data read operations for the first area of the first cell array block and a second area of a second cell array block are simultaneously executed, while the busy signal generation circuit generates a true busy signal, and then a read data output operation is executed for outputting the read out data of the first area held in the sense amplifier circuits to the chip external, and in a second read cycle selecting the second area in the second cell array block, after the busy signal generation circuit has output a dummy busy signal shorter in time length than the true busy signal without executing cell data read operation, a read data output operation is executed for outputting the read out data of the second area held in the sense amplifier circuits to the chip external.

REFERENCES:
patent: 5319595 (1994-06-01), Saruwatari
patent: 5523980 (1996-06-01), Sakui et al.
patent: 5986918 (1999-11-01), Lee
patent: 5986933 (1999-11-01), Takeuchi et al.
patent: 6903981 (2005-06-01), Futatsuyama et al.

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